Fix shuffle lowering code to stop creating temporary DAG nodes to do shuffle mask checks on. This seemed to be confusing things such that vector_shuffle ops to got through to iselection. This is another step towards removing the vector_shuffle handling patterns from isel.

llvm-svn: 150296

When using register masks, registers like %rip are clobbered by the
register mask. LICM should still be able to hoist instructions reading
%rip from a loop containing calls.

llvm-svn: 150288

Again the goal is to produce identical assembly with register mask
operands enabled.

llvm-svn: 150287

llvm-svn: 150286

Now that the clang driver passes the CPU and feature information to
the backend when processing assembly files (150273), this isn't necessary.

llvm-svn: 150274

It can be necessary to detach a register mask pointer from its
MachineOperand. This method is convenient for checking clobbered
physregs on a detached bitmask pointer.

llvm-svn: 150261

This makes global live range splitting behave identically with and
without register mask operands.

This is not necessarily the best way of using register masks for live
range splitting.  It would be more efficient to first split global live
ranges around calls (i.e., register masks), and reserve the fine grained
per-physreg interference guidance for global live ranges that do not
cross calls.

For now the goal is to produce identical assembly when enabling register
masks.

llvm-svn: 150259

llvm-svn: 150258

llvm-svn: 150251

This allows BBVectorize to check the "unknown instruction" list in the
alias sets. This is important to prevent instruction fusing from reordering
function calls. Resolves PR11920.

llvm-svn: 150250

llvm-svn: 150249

don't assume it is a boolean.

llvm-svn: 150247

Put instruction names into an indexed string table on the side, removing a pointer from MCInstrDesc.

Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't
have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64.

llvm-svn: 150245

llvm-svn: 150233

llvm-svn: 150228

llvm-svn: 150227

Creates a configurable regalloc pipeline.

Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa.

When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>.

CodeGen transformation passes are never "required" as an analysis

ProcessImplicitDefs does not require LiveVariables.

We have a plan to massively simplify some of the early passes within the regalloc superpass.

llvm-svn: 150226

llvm-svn: 150225

llvm-svn: 150224

rdar://10838899

llvm-svn: 150222

When checking a local live range for interference, restrict the binary
search to the single block.

llvm-svn: 150220

Provide API to get a list of register mask slots and bits in a basic
block.

llvm-svn: 150219

No looping and binary searches necessary.

Return a pointer to the containing block instead of just a bool.

llvm-svn: 150218

llvm-svn: 150214

Unify default construction of error_code uses on this idiom so that users don't
feel compelled to make static globals for naming convenience. (unfortunately I
couldn't make the original ctor private as some APIs don't return their result,
instead using an out parameter (that makes sense to default construct) - which
is a bit of a pity. I did, however, find/fix some cases of unnecessary default
construction of error_code before I hit the unfixable cases)

llvm-svn: 150197

This only adds the interference checks required for correctness.
We still need to take advantage of register masks for the
interference driven live range splitting.

llvm-svn: 150191

llvm-svn: 150183

llvm-svn: 150178

GlobalOpt runs early in the pipeline (before inlining) and complex class
hierarchies often introduce bitcasts or GEPs which weren't optimized away.
Teach it to ignore side-effect free instructions instead of depending on
other passes to remove them.

llvm-svn: 150174

Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.

llvm-svn: 150169

llvm-svn: 150167

Flatten some of the arrays in the X86 disassembler tables to reduce space needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953.

llvm-svn: 150161

Failure to preserve kills was causing LiveIntervals to miss some EFLAGS live
ranges. Unfortunately I've been unable to reduce a good test case yet.

llvm-svn: 150152

llvm-svn: 150150

llvm-svn: 150149

Split CodeGen into stages.
Distinguish between optimization and correctness.

llvm-svn: 150122

llvm-svn: 150121

If someone would prefer a clear name for the 'success' error_value we could
come up with one - potentially just a 'named constructor' style
'error_value::success()' to make this expression more self-documenting. If
I see this come up in other cases I'll certainly consider it.

One step along the way to resolving PR11944.

llvm-svn: 150120

This does make a difference, at least when using RABasic.

llvm-svn: 150118

Calls clobber the flags, but when using register masks there is no
EFLAGS<imp-def> operand.

llvm-svn: 150117