This is another one that doesn't matter much,
but uses the right GEP index types in the first
place.

llvm-svn: 189854

This doesn't actually matter, since alloca is always
0 address space, but this is more consistent.

llvm-svn: 189853

WIP: Refactor some code so that it can be called by more than just one method. No functionality change.

llvm-svn: 189849

This reverts commit r189648.

Fixes for the previously failing clang-side arm_neon_intrinsics test
cases will be checked in separately.

llvm-svn: 189841

This won't affect the kinds of hashes we test for as we actually
do hashing based on form and attribute. Change the fission-hash
testcase one last time to handle DW_AT_comp_dir.

llvm-svn: 189840

1) If the width of vectorization list candidate is bigger than vector reg width, we will break it down to fit the vector reg.
2) We do not vectorize the width which is not power of two.

The performance result shows it will help some spec benchmarks. mesa improved 6.97% and ammp improved 1.54%. 

llvm-svn: 189830

For now this just handles simple comparisons of an ANDed value with zero.
The CC value provides enough information to do any comparison for a
2-bit mask, and some nonzero comparisons with more populated masks,
but that's all future work.

llvm-svn: 189819

llvm-svn: 189796

Select condition shadow was being ignored resulting in false negatives.
This change OR-s sign-extended condition shadow into the result shadow.

llvm-svn: 189785

llvm-svn: 189780

llvm-svn: 189779

llvm-svn: 189768

Test cases adjusted accordingly.

This fixes rdar://14871821.

llvm-svn: 189766

What we really want is to enable Swift by default for *v7s triples (and there already seems to be some logic which attempts to do that). In that case the iOS version doesn't matter. 

llvm-svn: 189763

Test cases adjusted accordingly.

This fixes rdar://14871821.

llvm-svn: 189756

llvm-svn: 189742

llvm-svn: 189740

Specify GATHER/SCATTER as heavy instructions.

llvm-svn: 189736

This patch implements vector support for  select instruction and adds specific vector instructions : shuffle and insertelement. (tests are also included)
and functions lle_X_memset, lle_X_memcpy added.

Done by Veselov, Yuri (mailto:Yuri.Veselov@intel.com)

llvm-svn: 189735

printing routine. This is made harder to see due to the surprising
formatting, inconsistent brace usage, and repeated conditions that all
test the same thing.

The only "consequence" of this bug is re-assigning 'str' to an empty
string when computing the error string for an error number of 0 in the
event of a non-GNU strerror_r routine. So, nothing to see here other
than cleanup. It did help me find PR17055 in clang-format though.

llvm-svn: 189734

llvm-svn: 189729

llvm-svn: 189728

don't exist in libc. This is really not the right way to solve this problem;
but it's not clear to me at this time exactly what is the right way.
If we create stubs here, they will cause link errors because these functions
do not exist in libc.

llvm-svn: 189727

llvm-svn: 189726

The existing code missed some edge cases when e.g. we're going to emit sqrtf but
only the availability of sqrt was checked. This happens on odd platforms like
windows.

llvm-svn: 189724

There was one case that we could hit a DebugValue where I didn't think
to check. DebugValues are evil. No checkinable test case, sorry. It's
an obvious fix.

llvm-svn: 189717

Here are a few miscellaneous things to tidy up the PPC64 fast-isel
implementation.  I corrected a couple of commentary lapses, and added
documentation of future opportunities.  I also implemented
TargetMaterializeAlloca, which I somehow forgot when I split up the
original huge patch.

Finally, I decided to delete SelectCmp.  I hadn't previously hooked it
in to TargetSelectInstruction(), and when I did I realized it wasn't
serving any useful purpose.  This is only useful for compares that
don't feed a branch in the same block, and to handle that we would
have to have logic to interpret i1 as a condition register.  This
could probably be done, but would require Unseemly Hackery, and
honestly does not seem worth the hassle.

This ends the current patch series.

llvm-svn: 189715

This is the last substantive patch I'm planning for fast-isel in the
near future, adding fast selection of integer truncates.  There are
certainly more things that can be improved (many of which are called
out in FIXMEs), but for now we are catching most of the important
cases.

I'll document some of the remaining work in a cleanup patch shortly.

llvm-svn: 189706

llvm-svn: 189705

This patch adds fast-isel support for calls (but not intrinsic calls
or varargs calls).  It also removes a badly-formed assert.  There are
some new tests just for calls, and also for folding loads into
arguments on calls to avoid extra extends.

llvm-svn: 189701

llvm-svn: 189699

Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode.

llvm-svn: 189698

llvm-svn: 189697

 - We do some nasty things w.r.t. installing or overriding signal handlers in
   order to improve our crash recovery support or interaction with crash
   reporting software, and those things are not necessarily appropriate when
   LLVM is being linked into a client application that has its own ideas about
   how to do things. This gives those clients a way to disable that handling at
   build time.

 - Currently, the code this guards is all Apple specific, but other platforms
   might have the same concerns so I went for a more generic configure
   name. Someone who is more familiar with library embedding on Windows can
   handle choosing which of the Windows/Signals.inc behaviors might make sense
   to go under this flag.

 - This also fixes the proper autoconf'ing of ENABLE_BACKTRACES. The code
   expects it to be undefined when disabled, but the autoconf check was just
   defining it to 0.

llvm-svn: 189694

has hard float, when you compile the mips32 code you have to make sure
that it knows to compile any mips32 routines as hard float. I need to clean
up the way mips16 hard float is specified but I need to first think through
all the details. Mips16 always has a form of soft float, the difference being
whether the underlying hardware has floating point. So it's not really
necessary to pass the -soft-float to llvm since soft-float is always true
for mips16 by virtue of the fact that it will not register floating point
registers. By using this fact, I can simplify the way this is all handled.

llvm-svn: 189690

Remove redundant or bug-prone LiveInterval APIs.

llvm-svn: 189685

Yet another chunk of fast-isel code.  This one handles various
conversions involving floating-point.  (It also includes some
miscellaneous handling throughout the back end for LWA_32 and LWAX_32
that should have been part of the load-store patch.)

llvm-svn: 189677

llvm-svn: 189673

PR17026. Also avoid undefined shifts and shift amounts larger than 64 bits
(those are always undef because we can't represent integer types that large).

llvm-svn: 189672

Currently this is just the atom model with SSE4.2 enabled.

llvm-svn: 189669