llvm-svn: 77329

- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300

llvm-svn: 77275

llvm-svn: 77199

Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024

llvm-svn: 77020

llvm-svn: 77006

llvm-svn: 76954

llvm-svn: 76909

Also fixed up code to fully use the SoImm field for ADR on ARM mode.

llvm-svn: 76890

llvm-svn: 76600

llvm-svn: 76520

Minor code duplication cleanup.

llvm-svn: 76124

llvm-svn: 75576

llvm-svn: 75361

the previous RUN lines.  Hopefully this will be an inspiration for future
tests :)

llvm-svn: 75261

llvm-svn: 75218

llvm-svn: 75067

llvm-svn: 75012

Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.

llvm-svn: 75010

llvm-svn: 74946

llvm-svn: 74895

llvm-svn: 74889

llvm-svn: 74755

llvm-svn: 74740

llvm-svn: 74736

llvm-svn: 74696

llvm-svn: 74577

llvm-svn: 74555

llvm-svn: 74549

llvm-svn: 74500

llvm-svn: 74490

llvm-svn: 74468

llvm-svn: 74464

Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.

llvm-svn: 74423

After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420

When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.

llvm-svn: 74355

llvm-svn: 74345

llvm-svn: 74322

llvm-svn: 74321