llvm-svn: 133798

we cannot duplicate to every predecessor.

llvm-svn: 133797

llvm-svn: 133793

target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782

supports compact unwind info instead of having a separate flag indicating this.

llvm-svn: 133685

register allocation if it has a indirectbr or if we can duplicate it to
every predecessor.

This fixes the SingleSource/Benchmarks/Shootout-C++/matrix.cpp regression but
keeps the previous improvements to sunspider.

llvm-svn: 133682

llvm-svn: 133662

don't remove blocks that have their address taken.

llvm-svn: 133659

If the linker supports it, this will hold the CIE and FDE information in a
compact format. The implementation of the compact unwinding emission is coming
soon.

llvm-svn: 133658

Specifically, gcc.c-torture/compile/pr21356.c.

llvm-svn: 133646

is larger than the sum of the elements (including per-element padding).

llvm-svn: 133631

that takes an ArrayRef.

llvm-svn: 133615

be one with only one unconditional branch and no phis. Duplicating the phis in this case
is possible, but requeres liveness analysis or breaking edges.

llvm-svn: 133607

llvm-svn: 133569

llvm-svn: 133567

llvm-svn: 133561

There could be more than one DBG_VALUE instructions for variables where all of them have offset based on one register.

llvm-svn: 133560

explanation of what the EH table describes.

llvm-svn: 133559

1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8)
   => (bswap x) >> 16
2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8))
   => (rotl (bswap x) 16)

This allows us to eliminate most of the def : Pat patterns for ARM rev16
revsh instructions. It catches many more cases for ARM and x86.

rdar://9609108

llvm-svn: 133503

llvm-svn: 133446

* Don't introduce a duplicated bb in the CFG
* When making a branch unconditional, clear the PredCond array so that it
  is really unconditional.

llvm-svn: 133432

dragonegg buildbots back to life.  Original commit message:
Teach early dup how to duplicate basic blocks with one successor and only phi instructions
into more complex blocks.

llvm-svn: 133430

source vector type is to be split while the target vector is to be promoted.
(eg: <4 x i64> -> <4 x i8> )

llvm-svn: 133424

Fix MSVC build. next() function already exists in the MSVC headers. This create a overload conflict. Make sure we pick up the llvm one.

llvm-svn: 133416

into more complex blocks.

llvm-svn: 133415

all over the place in different styles and variants.  Standardize on two
preferred entrypoints: one that takes a StructType and ArrayRef, and one that
takes StructType and varargs.

In cases where there isn't a struct type convenient, we now add a
ConstantStruct::getAnon method (whose name will make more sense after a few
more patches land).  

It would be "really really nice" if the ConstantStruct::get and 
ConstantVector::get methods didn't make temporary std::vectors.

llvm-svn: 133412

const Constant *.

llvm-svn: 133400

llvm-svn: 133389

llvm-svn: 133388

instead of scalarizing, and doing an element-by-element truncat.

llvm-svn: 133382

much cleaner.

llvm-svn: 133364

llvm-svn: 133350

llvm-svn: 133348

llvm-svn: 133347

range without a libcall to a new mulo<mode> libcall
that we'd have to create.

Finishes the rest of rdar://9090077 and rdar://9210061

llvm-svn: 133318

llvm-svn: 133313

llvm-svn: 133307

llvm-svn: 133292

calls if we haven't been able to lower them any
other way.

Fixes rdar://9090077 and rdar://9210061

llvm-svn: 133288

The LSDA is a bit difficult for the non-initiated to read. Even with comments,
it's not always clear what's going on. This wraps the ASM streamer in a class
that retains the LSDA and then emits a human-readable description of what's
going on in it.

So instead of having to make sense of:

Lexception1:
        .byte   255
        .byte   155
        .byte   168
        .space  1
        .byte   3
        .byte   26
Lset0 = Ltmp7-Leh_func_begin1
      .long     Lset0
Lset1 = Ltmp812-Ltmp7
      .long     Lset1
Lset2 = Ltmp913-Leh_func_begin1
      .long     Lset2
      .byte     3
Lset3 = Ltmp812-Leh_func_begin1
      .long     Lset3
Lset4 = Leh_func_end1-Ltmp812
      .long     Lset4
      .long     0
      .byte     0
      .byte     1
      .byte     0
      .byte     2
      .byte     125
      .long     __ZTIi@GOTPCREL+4
      .long     __ZTIPKc@GOTPCREL+4

you can read this instead:

## Exception Handling Table: Lexception1
##  @LPStart Encoding: omit
##    @TType Encoding: indirect pcrel sdata4
##        @TType Base: 40 bytes
## @CallSite Encoding: udata4
## @Action Table Size: 26 bytes

## Action 1:
##   A throw between Ltmp7 and Ltmp812 jumps to Ltmp913 on an exception.
##     For type(s):  __ZTIi@GOTPCREL+4 __ZTIPKc@GOTPCREL+4
## Action 2:
##   A throw between Ltmp812 and Leh_func_end1 does not have a landing pad.

llvm-svn: 133286