into:

_t:
        movl 8(%esp), %ecx
        movl 4(%esp), %eax
        cmpl %ecx, %eax
        je LBB1_3       #bb17
LBB1_1: #bb
        cmpl %ecx, %eax
        jg LBB1_4       #cond_true
LBB1_2: #cond_false
        subl %eax, %ecx
        cmpl %ecx, %eax
        jne LBB1_1      #bb
LBB1_3: #bb17
        ret
LBB1_4: #cond_true
        subl %ecx, %eax
        cmpl %ecx, %eax
        jne LBB1_1      #bb
        jmp LBB1_3      #bb17

instead of:

_t:
        subl $4, %esp
        movl %esi, (%esp)
        movl 12(%esp), %ecx
        movl 8(%esp), %eax
        cmpl %ecx, %eax
        je LBB1_4       #bb17
LBB1_1: #bb.outer
        movl %ecx, %edx
        negl %edx
LBB1_2: #bb
        cmpl %ecx, %eax
        jle LBB1_5      #cond_false
LBB1_3: #cond_true
        addl %edx, %eax
        cmpl %ecx, %eax
        jne LBB1_2      #bb
LBB1_4: #bb17
        movl (%esp), %esi
        addl $4, %esp
        ret
LBB1_5: #cond_false
        movl %ecx, %edx
        subl %eax, %edx
        movl %eax, %esi
        addl %esi, %esi
        cmpl %ecx, %esi
        je LBB1_4       #bb17
LBB1_6: #cond_false.bb.outer_crit_edge
        movl %edx, %ecx
        jmp LBB1_1      #bb.outer

llvm-svn: 37252

llvm-svn: 37249

this case, the xform introduces an extra operation).  This compiles
PowerPC/compare-duplicate.ll into:

_test:
        subf r2, r3, r4
        cmplw cr0, r2, r3
        bne cr0, LBB1_2 ;F

instead of:

_test:
        slwi r2, r3, 1
        subf r3, r3, r4
        cmplw cr0, r4, r2
        bne cr0, LBB1_2 ;F

This is target independent of course.

llvm-svn: 37246

can't use getZExtValue() to extract the low order bits for each digit.
Instead, we need to access the low order word directly.

llvm-svn: 37242

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070514/049845.html

llvm-svn: 37240

llvm-svn: 37239

llvm-svn: 37237

llvm-svn: 37236

llvm-svn: 37235

llvm-svn: 37234

llvm-svn: 37233

llvm-svn: 37231

llvm-svn: 37230

llvm-svn: 37227

llvm-svn: 37204

llvm-svn: 37200

Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.

llvm-svn: 37199

llvm-svn: 37198

llvm-svn: 37197

llvm-svn: 37195

llvm-svn: 37194

llvm-svn: 37193

llvm-svn: 37192

llvm-svn: 37190

Test case at Transformations/SCCP/2007-05-16-InvokeCrash.ll

llvm-svn: 37185

in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm.  Ideally you would get cooperation
from the RA as well but this is not there yet.

llvm-svn: 37179

llvm-svn: 37175

Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector.

llvm-svn: 37173

llvm-svn: 37172

i128 integers.  The 64-bit masks are not wide enough to represent the results.
These should be converted to APInt someday.

llvm-svn: 37169

add expand support for ADDC/SUBC/ADDE/SUBE so we can codegen 128-bit add/sub on 32-bit (or less) targets

llvm-svn: 37168

cause other regressions.

llvm-svn: 37160

llvm-svn: 37159

llvm-svn: 37158

of verifying result values when debugging.

llvm-svn: 37156

llvm-svn: 37154

undefined behavior when the width > 64 bits.

llvm-svn: 37153

llvm-svn: 37141

llvm-svn: 37139

llvm-svn: 37138