instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728

extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.

This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.

llvm-svn: 37719

between SSE1 instructions and their respective SSE2 analogues.

llvm-svn: 37718

llvm-svn: 37717

llvm-svn: 37716

llvm-svn: 37705

TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704

llvm-svn: 37700

llvm-svn: 37669

llvm-svn: 37659

for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.

llvm-svn: 37656

llvm-svn: 37650

with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644

llvm-svn: 37643

Anton for half of this patch.

llvm-svn: 37641

Look for VECTOR_SHUFFLE that's identity operation on either LHS or RHS. This can happen before DAGCombiner catches it.

llvm-svn: 37636

llvm-svn: 37625

define double @test2(i64 %A) {
   %B = bitcast i64 %A to double
   ret double %B
}

$ llvm-as < t.ll | llc -march=x86-64

before:

         .align  4
         .globl  _test2
_test2:
         movd %rdi, %xmm0
         ret

after:

_test2:
         subq $8, %rsp
         movq %rdi, (%rsp)
         movsd (%rsp), %xmm0
         addq $8, %rsp
         ret

llvm-svn: 37617

llvm-svn: 37611

llvm-svn: 37606

llvm-svn: 37579

llvm-svn: 37578

implementation for x86.

llvm-svn: 37576

llvm-svn: 37574

llvm-svn: 37572

llvm-svn: 37571

llvm-svn: 37534

llvm-svn: 37533

llvm-svn: 37528

llvm-svn: 37527

llvm-svn: 37517

llvm-svn: 37516

Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks.

llvm-svn: 37484

llvm-svn: 37468

llvm-svn: 37466

- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.

llvm-svn: 37461

llvm-svn: 37437

llvm-svn: 37434

llvm-svn: 37419

switches.  There is one really easy isel thing here with tst we are not
getting.

llvm-svn: 37400