whether the extract instructions are available.

rdar://7956878

llvm-svn: 103277

llvm-svn: 103276

llvm-svn: 103272

llvm-svn: 103271

llvm-svn: 103269

patch by Peter Housel!

llvm-svn: 103267

llvm-svn: 103266

llvm-svn: 103264

DebugInfoFinder and iterates over all the contents calling print.

llvm-svn: 103262

llvm-svn: 103261

as MachineSink, but it isn't constrained by MachineInstr-level details.

llvm-svn: 103257

methods, and add dump functions implemented in terms of the print.

llvm-svn: 103254

Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.

llvm-svn: 103235

Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.

llvm-svn: 103234

llvm-svn: 103233

instruction, rather than a location near where the new instruction
is being inserted.

llvm-svn: 103232

lowered copies.

llvm-svn: 103228

llvm-svn: 103227

increase in the debug line info section, and it's causing
regressions in a gdb testsuite.

llvm-svn: 103226

Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.

llvm-svn: 103218

 - This fixes "leal 0, %eax", for example.

llvm-svn: 103205

llvm-svn: 103199

and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196

we don't currently support relaxing them.

llvm-svn: 103195

doesn't have to guess.

llvm-svn: 103194

llvm-svn: 103193

llvm-svn: 103185

(replacing the previous patch for the same issue).

llvm-svn: 103183

llvm-svn: 103181

llvm-svn: 103179

at the token level. Consider the following horrible test case:

  a = 1
  .globl $a
  movl ($a), %eax
  movl $a, %eax
  movl $$a, %eax

llvm-svn: 103178

Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.

llvm-svn: 103172

with the fix in 103157.

%reg1039:1<def> = VMOVS %S1<kill>, pred:14, pred:%reg0
is not coalescable since none of the super-registers of S1 are in reg1039's
register class: DPR_VFP2. But it is still a legal copy instruction so it should
not assert.

llvm-svn: 103170

llvm-svn: 103163

   Reverse-merging r103156 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMRegisterInfo.h
U    lib/Target/ARM/ARMBaseRegisterInfo.cpp
U    lib/Target/ARM/ARMBaseInstrInfo.cpp
U    lib/Target/ARM/ARMRegisterInfo.td

llvm-svn: 103159

automatic syscall restarting is disabled.

Also, fix the build on systems which don't define EWOULDBLOCK.

llvm-svn: 103158

llvm-svn: 103157

Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.

llvm-svn: 103156

llvm-svn: 103155

llvm-svn: 103154