Add a MachineFunction pass, which runs post register allocation, that turns subreg insert/extract instruction into register copies. This ensures correct code gen if the coalescer isn't able to remove all subreg instructions.

llvm-svn: 40521

llvm-svn: 40520

llvm-svn: 40518

llvm-svn: 40517

llvm-svn: 40516

llvm-svn: 40514

Fix infinite recursion for when extract_vector_elt is legal. Unfortunately no public targets use this code-path, so no test.

llvm-svn: 40510

llvm-svn: 40506

x86 target, replacing them with the new alignment attributes on memory
references.

llvm-svn: 40504

llvm-svn: 40503

llvm-svn: 40502

llvm-svn: 40501

llvm-svn: 40500

llvm-svn: 40499

llvm-svn: 40498

llvm-svn: 40497

llvm-svn: 40495

llvm-svn: 40494

Note: This has not yet been thoroughly tested.  Use at your own risk.

llvm-svn: 40489

AsmPrinter::doFinalization.

llvm-svn: 40487

This interface allows clients to inline bunch of functions with module
level call graph information.:wq

llvm-svn: 40486

llvm-svn: 40483

 - Split EH and debug infiormation
 - Make DwarfWriter more verbose in some cases

llvm-svn: 40481

llvm-svn: 40480

register instead of loading each element individually.

llvm-svn: 40478

NOTE: This has only been cursorily tested.  Expected improvements soon.

llvm-svn: 40476

llvm-svn: 40474

Pretty hackish, but code itself is dirty mess, so we won't make anything worse. :)

llvm-svn: 40472

load elimination code from RedundantLoadElimination.

llvm-svn: 40469

llvm-svn: 40464

llvm-svn: 40458

llvm-svn: 40457

llvm-svn: 40456

2. Fold an if statement into the Assert1 macro call.

llvm-svn: 40455

to use sret or inreg on the function. It is equally illegal to use noreturn
or nounwind on a parameter; they only go with the function. This patch
enforces these rules.

llvm-svn: 40453

llvm-svn: 40448

llvm-svn: 40445

llvm-svn: 40443

llvm-svn: 40441

llvm-svn: 40440