Commits · ea7bb570580d1a82c8654d0ee3ce6b0a4419a35b · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Jun 08, 2013
- ARM: fix VCVT decoding · ea7bb570
  Amaury de la Vieuville authored Jun 08, 2013
  ea7bb570
- Fix unused variable warning from my previous patch. · 60a24424
  JF Bastien authored Jun 08, 2013
  60a24424
- [mips] Use a helper function which compares the size of the source and · ae9d8e21
  Akira Hatanaka authored Jun 08, 2013
  ae9d8e21
- R600: Use a refined heuristic to choose when switching clause · d1a9d181
  Vincent Lejeune authored Jun 07, 2013
  d1a9d181
- R600: Anti dep better handled in tex clause · 4d143328
  Vincent Lejeune authored Jun 07, 2013
  4d143328
- Remember the anyext patterns. · fdc9d0a9
  Jakob Stoklund Olesen authored Jun 07, 2013
  fdc9d0a9
- Add missing zextloadi1 to i64 patterns. PR16721. · 9f812b97
  Jakob Stoklund Olesen authored Jun 07, 2013
  9f812b97
- Disallow i64 div/rem in PPC32 counter loops · fa5f6f74
  Hal Finkel authored Jun 07, 2013
  fa5f6f74
Jun 07, 2013
- Don't cache the instruction and register info from the TargetMachine, because · 999dacc5
  Bill Wendling authored Jun 07, 2013
  999dacc5
- Don't cache the instruction and register info from the TargetMachine, because · 8f26840c
  Bill Wendling authored Jun 07, 2013
  8f26840c
- Remove unused c'tor. · 52ca447f
  Bill Wendling authored Jun 07, 2013
  52ca447f
- R600: Fix calculation of stack offset in AMDGPUFrameLowering · d7458377
  Tom Stellard authored Jun 07, 2013
  d7458377
- Don't cache the instruction and register info from the TargetMachine, because · 637d97dd
  Bill Wendling authored Jun 07, 2013
  637d97dd
- R600: Rework subtarget info and remove AMDILDevice classes · a6c6e1bf
  Tom Stellard authored Jun 07, 2013
  a6c6e1bf
- Don't cache the instruction and register info from the TargetMachine, because · 6235c06f
  Bill Wendling authored Jun 07, 2013
  6235c06f
- Don't cache the instruction and register info from the TargetMachine, because · 37e9adb0
  Bill Wendling authored Jun 07, 2013
  37e9adb0
- R600: Fix the fetch limits for R600 generation GPUs · 3498e4ff
  Tom Stellard authored Jun 07, 2013
  3498e4ff
- R600: Move Subtarget feature definitions into AMDGPU.td · 99792774
  Tom Stellard authored Jun 07, 2013
  99792774
- R600: Remove unnecessary include · b0804ec2
  Tom Stellard authored Jun 07, 2013
  b0804ec2
- ARM FastISel integer sext/zext improvements · 06ce03d1
  JF Bastien authored Jun 07, 2013
  06ce03d1
- R600: Don't compare iterators of different maps. · 705d841b
  Benjamin Kramer authored Jun 07, 2013
  705d841b
- Vincent says the element is at most once in the vector, so we don't need a full std::remove. · ebe0be9c
  Benjamin Kramer authored Jun 07, 2013
  ebe0be9c
- Fix a typo in asm string of BP* family of instructions. With this fix · 158d8069
  Roman Divacky authored Jun 07, 2013
  158d8069
- R600: Fix a potential iterator invalidation issue. · a857fe11
  Benjamin Kramer authored Jun 07, 2013
  a857fe11
- R600: Remove an extra break in R600OptimizeVectorRegisters.cpp · 931bb768
  Vincent Lejeune authored Jun 07, 2013
  931bb768
- Fold variable that's only used in assert into the assert. · f0ec1994
  Benjamin Kramer authored Jun 07, 2013
  f0ec1994
- Don't cache the instruction and register info from the TargetMachine, because · 5e7656bf
  Bill Wendling authored Jun 07, 2013
  5e7656bf
- Don't cache the instruction and register info from the TargetMachine, because · ead89ef6
  Bill Wendling authored Jun 07, 2013
  ead89ef6
- Don't cache the instruction and register info from the TargetMachine, because · f5358213
  Bill Wendling authored Jun 07, 2013
  f5358213
- Don't cache the instruction and register info from the TargetMachine, because · 90bee83c
  Bill Wendling authored Jun 07, 2013
  90bee83c
- Don't cache the instruction and register info from the TargetMachine, because · 4a7a408e
  Bill Wendling authored Jun 07, 2013
  4a7a408e
- Don't cache the instruction and register info from the TargetMachine, because · f95178e6
  Bill Wendling authored Jun 07, 2013
  f95178e6
- Don't cache the instruction info and register info objects. · 496dc33b
  Bill Wendling authored Jun 07, 2013
  496dc33b
- ARM sched model: Use the right resources for DIV · c5893da3
  Arnold Schwaighofer authored Jun 07, 2013
  c5893da3
- ARM sched model: Add VFP div instruction on Swift · 5f0a2ce5
  Arnold Schwaighofer authored Jun 07, 2013
  5f0a2ce5
- ARM sched model: Add SIMD/VFP load/store instructions on Swift · a30936a3
  Arnold Schwaighofer authored Jun 07, 2013
  a30936a3
- [Sparc]: Use cmp instruction instead of subcc to compare integers. · dc82ac0d
  Venkatraman Govindaraju authored Jun 07, 2013
  dc82ac0d
- R600: Rewrite an awkward loop in R600MachineScheduler · 0030362e
  Vincent Lejeune authored Jun 06, 2013
  0030362e
Jun 06, 2013
- Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift" · e5f6a8f6
  Arnold Schwaighofer authored Jun 06, 2013
  e5f6a8f6
- ARM sched model: Add SIMD/VFP load/store instructions on Swift · cfe830dc
  Arnold Schwaighofer authored Jun 06, 2013
  cfe830dc