their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory

llvm-svn: 11995

llvm-svn: 11987

llvm-svn: 11984

switch statements in the constructors and simplifies the
implementation of the getUseType() member function. You will have to
specify defs using MachineOperand::Def instead of MOTy::Def though
(similarly for Use and UseAndDef).

llvm-svn: 11715

llvm-svn: 11393

llvm-svn: 11276

llvm-svn: 11274

llvm-svn: 11055

allocation.

llvm-svn: 10633

llvm-svn: 9903

Header files will be on the way.

llvm-svn: 9298

* Fix bug in the createNOP method, which was not marking the operands of the
  generated XCHG as useanddef.  I don't think this method is actually used,
  so it wasn't breaking anything, but it should be fixed anyway...

llvm-svn: 7539

llvm-svn: 6323

llvm-svn: 6320

llvm-svn: 5272

llvm-svn: 5102

* Expose information about implicit defs/uses of register through the
  MachineInstrInfo.h file.

llvm-svn: 4877

llvm-svn: 4826

llvm-svn: 4742

llvm-svn: 4741

llvm-svn: 4728

llvm-svn: 4442

llvm-svn: 4413

llvm-svn: 4410

llvm-svn: 4394

We can instruction select exactly one instruction 'ret void'.  Wow.

llvm-svn: 4284