No need to go up more levels. A def of a register also sets its sub-registers
(so if PhysRegInfo[SuperReg] is NULL, it means SuperReg's super registers are
not previously defined).

llvm-svn: 47399

rename QualType::getQualifiers to getCVRQualifiers.
Add some fixme's and clean up some code relevant to qualifiers.
Change ASQualType to contain a Type* instead of a QualType.  
Any CVR qualifiers should be on the outer qual type.

llvm-svn: 47398

llvm-svn: 47397

llvm-svn: 47396

llvm-svn: 47395

llvm-svn: 47394

consistency.

llvm-svn: 47393

llvm-svn: 47392

llvm-svn: 47391

llvm-svn: 47390

llvm-svn: 47389

llvm-svn: 47388

llvm-svn: 47387

llvm-svn: 47386

llvm-svn: 47385

and splitting extract_subvector.  This fixes nine
"make check" testcases, for example
2008-02-04-ExtractSubvector.ll and (partially)
CodeGen/Generic/vector.ll.

llvm-svn: 47384

llvm-svn: 47383

llvm-svn: 47382

llvm-svn: 47381

llvm-svn: 47380

llvm-svn: 47379

llvm-svn: 47378

llvm-svn: 47377

llvm-svn: 47376

llvm-svn: 47375

llvm-svn: 47374

llvm-svn: 47373

llvm-svn: 47372

llvm-svn: 47371

llvm-svn: 47370

llvm-svn: 47369

llvm-svn: 47368

llvm-svn: 47367

Added two "FIXMEs" for code that looks dubious to me (but I could be
wrong).

llvm-svn: 47366

llvm-svn: 47365

llvm-svn: 47364

llvm-svn: 47363

changes. (Sorry for any formatting changes that creeped in.)

llvm-svn: 47362

llvm-svn: 47361

Parse reversed smax and umax as smin and umin and express them with negative
or binary-not SCEVs (which are really just subtract under the hood).

Parse 'xor %x, -1' as (-1 - %x).

Remove dead code (ConstantInt::get always returns a ConstantInt).

Don't use getIntegerSCEV(-1, Ty). The first value is an int, then it gets
passed into a uint64_t. Instead, create the -1 directly from
ConstantInt::getAllOnesValue().

llvm-svn: 47360