else in X86), and add support for pavgusb.  This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.

If someone else is interested in banging out the rest of the 3DNow! 
instructions, it should be quite easy now.

llvm-svn: 115466

With this patch in

movq    $foo, foo(%rip)
foo:
.long   foo

We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.

llvm-svn: 115134

  lib/Target/X86/X86MCCodeEmitter.cpp: 190: error: suggest parentheses around '&&' within '||'

llvm-svn: 115064

order as cctools for diffability.

llvm-svn: 115022

are defined to emit the 0x67 prefix byte.  rdar://8482675

llvm-svn: 115021

What a weird instruction.

llvm-svn: 114190

llvm-svn: 112128

call and jumps.

llvm-svn: 111496

llvm-svn: 111102

llvm-svn: 111082

llvm-svn: 109002

llvm-svn: 108983

Add the x86 VEX_L form to handle special cases where VEX_L must be set.

llvm-svn: 108274

notes:
- The instructions are being added with dummy placeholder patterns using some 256
  specifiers, this is not meant to work now, but since there are some multiclasses
  generic enough to accept them,  when we go for codegen, the stuff will be already
  there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
  file.

llvm-svn: 107996

fields to use. 

llvm-svn: 107952

llvm-svn: 107942

llvm-svn: 107939

llvm-svn: 107937

like all other instructions, even though a segment is not
allowed.  This resolves a bunch of gross hacks in the 
encoder and makes LEA more consistent with the rest of the
instruction set.

No functionality change.

llvm-svn: 107934

X86 memory operand.

llvm-svn: 107925

in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax

This fixes rdar://8127102.  I have several cleanup patches coming
next.

llvm-svn: 107917

llvm-svn: 107826

in the integrated assembler.  Still some discussion to be
done.

llvm-svn: 107825

llvm-svn: 107717

Update VEX encoding to support those new instructions

llvm-svn: 107715

llvm-svn: 107599

- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode

llvm-svn: 107523

- Add AVX SSE2 Move doubleword and quadword instructions.
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.

llvm-svn: 107365

- Add VEX encoding bits to x86 MRM0r-MRM7r

llvm-svn: 107238

Add AVX ld/st XCSR register.
Add VEX encoding bits for MRMXm x86 form

llvm-svn: 107204

Add several AVX MOV flavors
Support VEX encoding for MRMDestReg

llvm-svn: 106912

llvm-svn: 106906

Support VEX encoding for MRMDestReg

llvm-svn: 106896

- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.

llvm-svn: 106787

llvm-svn: 106588

llvm-svn: 106365

segment prefixes.  Daniel wrote most of this patch.

llvm-svn: 106364

Handle OpSize TSFlag for AVX

llvm-svn: 105869

llvm-svn: 105860

Introduce the VEX_X field

llvm-svn: 105859