The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.

Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics. 

MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces.  Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.

The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.

llvm-svn: 115243

llvm-svn: 113409

  - Do not clobber al during variadic calls, this is AMD64 ABI-only feature
  - Emit wincall64, where necessary
Patch by Cameron Esfahani!

llvm-svn: 111289

llvm-svn: 111182

llvm-svn: 110937

term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.

llvm-svn: 110897

llvm-svn: 110359

llvm-svn: 109154

asmprinter or mangler around.  This is option #B for killing off 
X86InstrInfo::GetInstSizeInBytes.  Option #A (killing 
"needsexactsize") was sent for consideration to llvmdev.

llvm-svn: 109056

llvm-svn: 108955

llvm-svn: 108952

llvm-svn: 108950

llvm-svn: 108949

llvm-svn: 108947

llvm-svn: 108945

of AsmPrinter and InstLowering into libx86 and out of the
asmprinter subdirectory.  Now X86/AsmPrinter just depends on
MC stuff, not all of codegen and LLVM IR.

llvm-svn: 108782

llvm-svn: 108368

jumps where possible and turning the TAILCALL marker in the instruction
asm string into a proper comment.

This eliminates a FIXME and is on the path to finishing:
rdar://7639610 - eliminate encoding and asm info for TAILJMPd TAILJMPr TAILJMPn, etc.

However, I can't eliminate the encodings for these instructions because the JIT
still exists and has its own copy of the encoder, sigh.

llvm-svn: 107946

llvm-svn: 107939

like all other instructions, even though a segment is not
allowed.  This resolves a bunch of gross hacks in the 
encoder and makes LEA more consistent with the rest of the
instruction set.

No functionality change.

llvm-svn: 107934

llvm-svn: 107818

llvm-svn: 107678

TLVP:

movl _a@TLVP, %eax

Daniel: Please review if you get a chance.
llvm-svn: 106194

llvm-svn: 105381

prefix byte problem as in r104062.
 - As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.

llvm-svn: 104120

CALL64pcrel32, for the same reason.

llvm-svn: 104116

llvm-svn: 104112

avoid same prefix byte problem as in r104062.

llvm-svn: 104108

The register use operands (e.g. the first argument is passed in a 
register) is currently being modeled as a normal register use,
instead of correctly being an implicit use.  This causes the operand
to get propagated onto the mcinst, which was causing the encoder to
emit a rex prefix byte, which generates an invalid call.

This fixes rdar://7998435

llvm-svn: 104062

  X86::ADC32ri $0, %eax
to
  X86::ADC32i32 $0

llvm-svn: 104030

llvm-svn: 103276

	##DEBUG_VALUE: runOnMachineFunction:this <- RDI+0
	##DEBUG_VALUE: runOnMachineFunction:fn <- RSI+0
	##DEBUG_VALUE: DeadDefs <- undef ## SimpleRegisterCoalescing.cpp:2706
	##DEBUG_VALUE: getRegInfo:this <- [%rsp+$56]+$0
	##DEBUG_VALUE: getTarget:this <- [%rsp+$56]+$0

llvm-svn: 102655

llvm-svn: 102486

llvm-svn: 101639

llvm-svn: 101085

into AsmPrinter.  Target-dependent form is still generated
by FastISel and still handled in X86 code.

llvm-svn: 100596

llvm-svn: 100578

There is probably a more elegant way to do this.

llvm-svn: 100573

llvm-svn: 100342

streamerized for everything.

llvm-svn: 100316