llvm-svn: 112659

Reserved registers are unpredictable, and are treated as always live by machine
DCE.

Allocatable registers are never reserved, and can be used for virtual registers.

Unreserved, unallocatable registers can not be used for virtual registers, but
otherwise behave like a normal allocatable register. Most targets only have
the flag register in this set.

llvm-svn: 112649

llvm-svn: 112632

llvm-svn: 112631

Remember byval argument's frame index during argument lowering and use this info to emit debug info.
Fixes Radar 8367011.

llvm-svn: 112623

  1. Allocate them in the entry block of the function to enable function-wide
     re-use. The instructions to create them should be re-materializable, so
     there shouldn't be additional cost compared to creating them local
     to the basic blocks where they are used.
  2. Collect all of the frame index references for the function and sort them
     by the local offset referenced. Iterate over the sorted list to
     allocate the virtual base registers. This enables creation of base
     registers optimized for positive-offset access of frame references.
     (Note: This may be appropriate to later be a target hook to do the
     sorting in a target appropriate manner. For now it's done here for
     simplicity.)

llvm-svn: 112609

any more.  I plan to reimplement alloca promotion using SSAUpdater later.
It looks like Bill's URoR logic really always needs domtree, so the pass
now always asks for domtree info.

llvm-svn: 112597

llvm-svn: 112584

llvm-svn: 112583

llvm-svn: 112571

Eventually, we want to disable physreg coalescing completely, and let the
register allocator do its job using hints.

This option makes it possible to measure the impact of disabling physreg
coalescing.

llvm-svn: 112567

1) nuke ConstDataCoalSection, which is dead.
2) revise my previous patch for rdar://8018335,
  which was completely wrong.  Specifically, it doesn't 
  make sense to mark __TEXT,__const_coal as PURE_INSTRUCTIONS,
  because it is for readonly data.  templates (it turns out)
  go to const_coal_nt.  The real fix for rdar://8018335 was
  to give ConstTextCoalSection a section kind of ReadOnly 
  instead of Text.

llvm-svn: 112496

llvm-svn: 112463

said (physical) register.

llvm-svn: 112461

llvm-svn: 112459

instead of PromoteMemToReg.  This allows it to stop using DF and DT,
eliminating a computation of DT and DF from clang -O3.  Clang is now
down to 2 runs of DomFrontier.

llvm-svn: 112457

llvm-svn: 112455

being actively maintained, improved, or extended.

llvm-svn: 112356

llvm-svn: 112354

doesn't currently support dealing with this.

llvm-svn: 112341

llvm-svn: 112340

llvm-svn: 112305

llvm-svn: 112287

llvm-svn: 112242

to try to re-use scavenged frame index reference registers. rdar://8277890

llvm-svn: 112241

llvm-svn: 112238

virtual base registers handle this function, and more. A bit more cleanup
to do on the interface to eliminateFrameIndex() after this.

llvm-svn: 112237

llvm-svn: 112216

llvm-svn: 112215

llvm-svn: 112213

Donot forget to resolve dangling debug info in a case where virtual register, used for a value, is initialized after a dbg intrinsic is seen.

llvm-svn: 112207

llvm-svn: 112175

llvm-svn: 112171

llvm-svn: 112155

llvm-svn: 112104

expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats.  This
affects two places in the code: handling cross block values and handling
function return and arguments.  Since vectors are already widened by 
legalizetypes, this gives us much better code and unblocks x86-64 abi
and SPU abi work.

For example, this (which is a silly example of a cross-block value):
define <4 x float> @test2(<4 x float> %A) nounwind {
 %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
 %C = fadd <2 x float> %B, %B
  br label %BB
BB:
 %D = fadd <2 x float> %C, %C
 %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ret <4 x float> %E
}

Now compiles into:

_test2:                                 ## @test2
## BB#0:
 addps %xmm0, %xmm0
 addps %xmm0, %xmm0
 ret

previously it compiled into:

_test2:                                 ## @test2
## BB#0:
 addps %xmm0, %xmm0
 pshufd $1, %xmm0, %xmm1
                                        ## kill: XMM0<def> XMM0<kill> XMM0<def>
 insertps $0, %xmm0, %xmm0
 insertps $16, %xmm1, %xmm0
 addps %xmm0, %xmm0
 ret

This implements rdar://8230384

llvm-svn: 112101

llvm-svn: 112086

llvm-svn: 112085

llvm-svn: 112084

no functionality change.

llvm-svn: 111994