Tail duplication produces lots of identical phi nodes in different basic
blocks. Teach PHIElimination to reuse the join registers when lowering a phi
node that is identical to an already lowered node. This saves virtual
registers, and more importantly it avoids creating copies the the coalescer
doesn't know how to eliminate.

Teach LiveIntervalAnalysis about the phi joins with multiple uses.

This patch significantly reduces code size produced by -pre-regalloc-taildup.

llvm-svn: 91549

problem", this broke llvm-gcc bootstrap for release builds on
x86_64-apple-darwin10.

This reverts commit db22309800b224a9f5f51baf76071d7a93ce59c9.

llvm-svn: 91534

this", this broke llvm-gcc bootstrap for release builds on
x86_64-apple-darwin10.

llvm-svn: 91533

miscompile (i386.o miscompares) but it happens both with and without
this patch.

llvm-svn: 91532

SmallVectorBase::grow_pod out of line, finally satisfying PR3758.

llvm-svn: 91529

is not used by anything performance sensitive, so just use std::string.

llvm-svn: 91528

a fixed size buffer is perfectly fine.

llvm-svn: 91527

llvm-svn: 91524

MDNodes that refer to an instruction are local to a function; in that case, explicitly keep track of the function they are local to

llvm-svn: 91497

bytes of Inst to 0x0000 for the benefit of the Thumb decoder.

llvm-svn: 91496

llvm-svn: 91489

Will reapply with a fix when I get a chance.

llvm-svn: 91486

in local register allocator.  If a reg-reg copy has a phys reg
input and a virt reg output, and this is the last use of the phys
reg, assign the phys reg to the virt reg.  If a reg-reg copy has
a phys reg output and we need to reload its spilled input, reload
it directly into the phys reg than passing it through another reg.

Following 76208, there is sometimes no dependency between the def of
a phys reg and its use; this creates a window where that phys reg
can be used for spilling (this is true in linear scan also).  This
is bad and needs to be fixed a better way, although 76208 works too
well in practice to be reverted.  However, there should normally be
no spilling within inline asm blocks.  The patch here goes a long way
towards making this actually be true.

llvm-svn: 91485

llvm-svn: 91481

enclosing namespace.  Caught by clang++.

llvm-svn: 91480

llvm-svn: 91479

llvm-svn: 91477

llvm-svn: 91475

remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface.  It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.

llvm-svn: 91464

found last time.  Instead of trying to modify the IR while iterating over it,
I've change it to keep a list of WeakVH references to dead instructions, and
then delete those instructions later.  I also added some special case code to
detect and handle the situation when both operands of a memcpy intrinsic are
referencing the same alloca.

llvm-svn: 91459

real data, not metadata) and fix DbgInfoPrinter to not abuse
GetConstantStringInfo.

llvm-svn: 91444

llvm-svn: 91440

llvm-svn: 91438

llvm-svn: 91434

llvm-svn: 91432

llvm-svn: 91428

isPodLike type trait.  This is a generally useful type trait for
more than just DenseMap, and we really care about whether something
acts like a pod, not whether it really is a pod.

llvm-svn: 91421

llvm-svn: 91417

llvm-svn: 91410

llvm-svn: 91405

1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest.
2. If the shift is a left shift, make sure the original shift cannot shift out bits.

llvm-svn: 91399

clang enforces it.

llvm-svn: 91397

stuff isn't used just yet.

We want to model the GCC `-fno-schedule-insns' and `-fno-schedule-insns2'
flags. The hypothesis is that the people who use these flags know what they are
doing, and have hand-optimized the C code to reduce latencies and other
conflicts.

The idea behind our scheme to turn off scheduling is to create a map "on the
side" during DAG generation. It will order the nodes by how they appeared in the
code. This map is then used during scheduling to get the ordering.

llvm-svn: 91392

Tail duplication should zap a copy it inserted for SSA update if the copy is the only use of its source.

llvm-svn: 91390

llvm-svn: 91381

llvm-svn: 91380

llvm-svn: 91378

llvm-svn: 91377

$ svn merge -c -91161 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r91161 into '.':
U    lib/CodeGen/BranchFolding.cpp
U    lib/CodeGen/MachineBasicBlock.cpp
$ svn merge -c -91113 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r91113 into '.':
G    lib/CodeGen/MachineBasicBlock.cpp
$ svn merge -c -91101 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r91101 into '.':
U    include/llvm/CodeGen/MachineBasicBlock.h
G    lib/CodeGen/MachineBasicBlock.cpp
$ svn merge -c -91092 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r91092 into '.':
G    include/llvm/CodeGen/MachineBasicBlock.h
G    lib/CodeGen/MachineBasicBlock.cpp

llvm-svn: 91376

llvm-svn: 91371