llvm-svn: 60433

llvm-svn: 60432

llvm-svn: 60409

llvm-svn: 60406

llvm-svn: 60392

llvm-svn: 60391

llvm-svn: 60381

MERGE_VALUES node with only one operand, so get
rid of special code that only existed to handle
that possibility.

llvm-svn: 60349

ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.

llvm-svn: 60348

as unsigned divisions.  Same caveats as before.

llvm-svn: 60284

multiplies.

Some more cleverness would be nice, though. It would be nice if we 
could do this transformation on illegal types.  Also, we would 
prefer a narrower constant when possible so that we can use a narrower
multiply, which can be cheaper.

llvm-svn: 60283

nearby FIXME.

I'm not sure what the right way to fix the Cell test was; if the 
approach I used isn't okay, please let me know.

llvm-svn: 60277

Despite changing the order of evaluation, this doesn't actually change the
meaning of the statement.

llvm-svn: 60177

llvm-svn: 60149

llvm-svn: 60141

llvm-svn: 60137

llvm-svn: 60102

and the LiveInterval.h top-level comment and accordingly. This fixes blocks
having spurious live-in registers in boundary cases.

llvm-svn: 60092

llvm-svn: 60043

llvm-svn: 60041

llvm-svn: 60016

llvm-svn: 60015

if the operands have the same sign and the sum has sign opposite to that of the
operands."

llvm-svn: 60014

introduce any new spilling; it just uses unused registers.

Refactor the SUnit topological sort code out of the RRList scheduler and
make use of it to help with the post-pass scheduler.

llvm-svn: 59999

- Mark "add with overflow" as having a custom lowering for X86. Give it a null
  lowering representation for now.

llvm-svn: 59971

to removePred because an SUnit can both data-depend and anti-depend
on the same SUnit.

llvm-svn: 59969

llvm-svn: 59968

obscure tail-merging opportunities.

llvm-svn: 59967

llvm-svn: 59961

(this doesn't happen that often, since most code
does not use illegal types) then follow it by a
DAG combiner run that is allowed to generate
illegal operations but not illegal types.  I didn't
modify the target combiner code to distinguish like
this between illegal operations and illegal types,
so it will not produce illegal operations as well
as not producing illegal types.

llvm-svn: 59960

llvm-svn: 59952

llvm-svn: 59926

practice these booleans are mostly produced by SetCC,
however the concept is more general.

llvm-svn: 59911

Added check to avoid generating extract subvector beyond the end of the vector when normalizing vector shuffles.

llvm-svn: 59900

llvm-svn: 59872

"It simplifies the type legalization part a bit, and produces better code by
teaching SelectionDAG about the extra bits in an i8 SADDO/UADDO node.  In
essence, I spontaneously decided that on x86 this i8 boolean result would be
either 0 or 1, and on other platforms 0/1 or 0/-1, depending on whether the
platform likes it's boolean zero extended or sign extended."

llvm-svn: 59864

- Add "promote integer type" stuff to the legalizer for these nodes.

llvm-svn: 59847

llvm-svn: 59841

llvm-svn: 59837

llvm-svn: 59836