This compiles Regression/CodeGen/X86/or-branch.ll into:

_foo:
        subl $12, %esp
        call L_bar$stub
        movl 20(%esp), %eax
        movl 16(%esp), %ecx
        cmpl $5, %eax
        jl LBB1_1       #cond_true
LBB1_3: #entry
        testl %ecx, %ecx
        jne LBB1_2      #UnifiedReturnBlock
LBB1_1: #cond_true
        call L_bar$stub
        addl $12, %esp
        ret
LBB1_2: #UnifiedReturnBlock
        addl $12, %esp
        ret

instead of:

_foo:
        subl $12, %esp
        call L_bar$stub
        movl 20(%esp), %eax
        movl 16(%esp), %ecx
        cmpl $4, %eax
        setg %al
        testl %ecx, %ecx
        setne %cl
        testb %cl, %al
        jne LBB1_2      #UnifiedReturnBlock
LBB1_1: #cond_true
        call L_bar$stub
        addl $12, %esp
        ret
LBB1_2: #UnifiedReturnBlock
        addl $12, %esp
        ret

And on ppc to:

        cmpwi cr0, r29, 5
        blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
        cmplwi cr0, r30, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

instead of:

        cmpwi cr7, r4, 4
        mfcr r2
        addic r4, r3, -1
        subfe r30, r4, r3
        rlwinm r29, r2, 30, 31, 31
        and r2, r29, r30
        cmplwi cr0, r2, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

llvm-svn: 31230

llvm-svn: 31229

llvm-svn: 31228

llvm-svn: 31227

llvm-svn: 31226

llvm-svn: 31225

llvm-svn: 31224

llvm-svn: 31223

llvm-svn: 31222

llvm-svn: 31221

llvm-svn: 31220

llvm-svn: 31219

llvm-svn: 31218

llvm-svn: 31217

llvm-svn: 31215

llvm-svn: 31214

llvm-svn: 31211

llvm-svn: 31210

llvm-svn: 31209

llvm-svn: 31208

llvm-svn: 31207

llvm-svn: 31206

name supplied by linker to construct temp bc file names.

Remove tabs.

llvm-svn: 31205

   InsertNewInstBefore(new CastInst(Val, ValTy, Val->GetName()), I)
into:
   InsertCastBefore(Val, ValTy, I)

llvm-svn: 31204

llvm-svn: 31203

llvm-svn: 31202

llvm-svn: 31201

llvm-svn: 31200

llvm-svn: 31199

vector of FP types.

llvm-svn: 31198

llvm-svn: 31197

llvm-svn: 31196

Make necessary changes to support DIV -> [SUF]Div. This changes llvm to
have three division instructions: signed, unsigned, floating point. The
bytecode and assembler are bacwards compatible, however.

llvm-svn: 31195

produce an EQ property.

llvm-svn: 31193

the call the pass2.

llvm-svn: 31192

llvm-svn: 31191

mistake that I made in the file too.

llvm-svn: 31190

Fix and comment the "or", "and" and "xor" transformations.

llvm-svn: 31189

llvm-svn: 31188

llvm-svn: 31187