When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.

llvm-svn: 138862

It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.

The failing test case is complicated, I am working on a reduction.

<rdar://problem/10044201>

llvm-svn: 138861

llvm-svn: 138859

llvm-svn: 138858

Make sure we don't crash when -miphoneos-version-min is specified on x86.  Hopefully this will fix gcc testsuite failures.

llvm-svn: 138856

Patch by Sanjoy Das

llvm-svn: 138853

On Python-w32 with mingw msys bash, %T was replaced to "x:\foo\bar...". msys bash cannot handle DOSish paths.

llvm-svn: 138852

- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
  and update a testcase to check it properly

llvm-svn: 138851

llvm-svn: 138850

whenever AVX is enabled.

llvm-svn: 138849

llvm-svn: 138848

llvm-svn: 138846

llvm-svn: 138845

llvm-svn: 138843

ssa, so it has to be run really early in the pipeline. Any replacement
should probably use the SSAUpdater.

llvm-svn: 138841

Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE.  Discovered by roundtrip testing.

llvm-svn: 138840

llvm-svn: 138837

llvm-svn: 138836

llvm-svn: 138835

Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping.

llvm-svn: 138834

llvm-svn: 138833

llvm-svn: 138832

llvm-svn: 138831

llvm-svn: 138830

llvm-svn: 138829

disabled.

llvm-svn: 138826

In the case of EDInstInfo, this would actually cause a bug when -1 became 255
and was then compared >=0 in llvm-mc/Disassembler.cpp.

llvm-svn: 138825

llvm-svn: 138823

llvm-svn: 138822

Patch by Sanjoy Das.

llvm-svn: 138820

llvm-svn: 138819

code is inserted to first check if the current stacklet has enough
space. If so, space is allocated by simply decrementing the stack
pointer. Otherwise a runtime routine (__morestack_allocate_stack_space
in libgcc) is called which allocates the required memory from the
heap.

Patch by Sanjoy Das.

llvm-svn: 138818

from DYNAMIC_STACKALLOC.

Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which
will match X86SegAlloca (based on word size) are also added.  They
will be custom emitted to inject the actual stack handling code.

Patch by Sanjoy Das.

llvm-svn: 138814

X86. Modify the pass added in the previous patch to call this new
code.

This new prologues generated will call a libgcc routine (__morestack)
to allocate more stack space from the heap when required

Patch by Sanjoy Das.

llvm-svn: 138812

-segmented-stacks.
Patch by Sanjoy Das!

llvm-svn: 138811

Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.

llvm-svn: 138810

When walking backwards to eliminate final stores to allocas at the end of a function, encountering an unrelated store should not cause us to give up like encountering a load does.

llvm-svn: 138809

llvm-svn: 138807

llvm-svn: 138806

Eli added this in revision 132695.

llvm-svn: 138805