llvm-svn: 78793

"inlineasmstart/end" strings so that the contents of the directive
are separate from the comment character.  This lets elf targets
get #APP/#NOAPP for free even if they don't use "#" as the comment
character.  This also allows hoisting the darwin stuff up to the
shared TAI class.

llvm-svn: 78737

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

LLVMTargetMachine ctor.  It is currently unused.

llvm-svn: 78711

llvm-svn: 78610

Start moving TargetLowering away from using full MVTs and towards SimpleValueType, which will simplify the privatization of IntegerType in the future.

llvm-svn: 78584

llvm-svn: 78506

error condition get trapped with an assert.

llvm-svn: 78449

Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.

This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.

This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.

llvm-svn: 78142

llvm-svn: 78105

The only exception is CC.

llvm-svn: 78089

llvm-svn: 78020

Thanks Chris.

llvm-svn: 77987

 - The C, C++, MSIL, and Mips backends still need the module.

llvm-svn: 77927

Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.

llvm-svn: 77918

__builtin_bfin_ones does the same as ctpop, so it can be implemented in the front-end.

__builtin_bfin_loadbytes loads from an unaligned pointer with the disalignexcpt instruction. It does the same as loading from a pointer with the low bits masked. It is better if the front-end creates a masked load. We can always instruction select the masked to disalignexcpt+load.

We keep csync/ssync/idle. These intrinsics represent instructions that need workarounds for some silicon revisions. We may even want to convert inline assembler to intrinsics to enable the workarounds.

llvm-svn: 77917

llvm-svn: 77903

This is just the framework to identify the needed workarounds. They are not actually implemented.

llvm-svn: 77902

We use the same constraints as GCC, including those that are slightly insane for inline assembler.

llvm-svn: 77899

Generate code for the Blackfin family of DSPs from Analog Devices:

  http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html
  
We aim to be compatible with the exsisting GNU toolchain found at:

  http://blackfin.uclinux.org/gf/project/toolchain
  
The back-end is experimental.

llvm-svn: 77897