Commits · ee4ca9ba0e249443a4c772a98635c69d39687819 · Roger Ferrer / llvm-epi-0.8

Jun 07, 2013
- R600: Fix a potential iterator invalidation issue. · a857fe11
  Benjamin Kramer authored 11 years ago
```
As a bonus this reduces the loop from O(n^2) to O(n).

llvm-svn: 183532
```
  a857fe11
- R600: Remove an extra break in R600OptimizeVectorRegisters.cpp · 931bb768
  Vincent Lejeune authored 11 years ago
```
llvm-svn: 183528
```
  931bb768
- Fold variable that's only used in assert into the assert. · f0ec1994
  Benjamin Kramer authored 11 years ago
```
Avoids unused variable warnings in Release builds.

llvm-svn: 183512
```
  f0ec1994
- Don't cache the instruction and register info from the TargetMachine, because · 5e7656bf
  Bill Wendling authored 11 years ago
```
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183494
```
  5e7656bf
- Don't cache the instruction and register info from the TargetMachine, because · ead89ef6
  Bill Wendling authored 11 years ago
```
the internals of TargetMachine could change.

llvm-svn: 183493
```
  ead89ef6
- Don't cache the instruction and register info from the TargetMachine, because · f5358213
  Bill Wendling authored 11 years ago
```
the internals of TargetMachine could change.

llvm-svn: 183492
```
  f5358213
- Don't cache the instruction and register info from the TargetMachine, because · 90bee83c
  Bill Wendling authored 11 years ago
```
the internals of TargetMachine could change.

llvm-svn: 183491
```
  90bee83c
- Don't cache the instruction and register info from the TargetMachine, because · 4a7a408e
  Bill Wendling authored 11 years ago
```
the internals of TargetMachine could change.

llvm-svn: 183490
```
  4a7a408e
- Don't cache the instruction and register info from the TargetMachine, because · f95178e6
  Bill Wendling authored 11 years ago
```
the internals of TargetMachine could change.

llvm-svn: 183488
```
  f95178e6
- Don't cache the instruction info and register info objects. · 496dc33b
  Bill Wendling authored 11 years ago
```
These objects are internal to the TargetMachine object and may change.

llvm-svn: 183485
```
  496dc33b
- ARM sched model: Use the right resources for DIV · c5893da3
  Arnold Schwaighofer authored 11 years ago
```
llvm-svn: 183477
```
  c5893da3
- ARM sched model: Add VFP div instruction on Swift · 5f0a2ce5
  Arnold Schwaighofer authored 11 years ago
```
Reapply 183271.

llvm-svn: 183472
```
  5f0a2ce5
- ARM sched model: Add SIMD/VFP load/store instructions on Swift · a30936a3
  Arnold Schwaighofer authored 11 years ago
```
Reapply 183270 again (because three is a magic number).

This should now no longer seg fault after r183459.

llvm-svn: 183464
```
  a30936a3
- [Sparc]: Use cmp instruction instead of subcc to compare integers. · dc82ac0d
  Venkatraman Govindaraju authored 11 years ago
```
llvm-svn: 183463
```
  dc82ac0d
- R600: Rewrite an awkward loop in R600MachineScheduler · 0030362e
  Vincent Lejeune authored 11 years ago
```
llvm-svn: 183458
```
  0030362e
Jun 06, 2013
- Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift" · e5f6a8f6
  Arnold Schwaighofer authored 11 years ago
```
Breaks linux build bots (I thought the problem was something else).

llvm-svn: 183447
```
  e5f6a8f6
- ARM sched model: Add SIMD/VFP load/store instructions on Swift · cfe830dc
  Arnold Schwaighofer authored 11 years ago
```
Reapply 183270.

llvm-svn: 183445
```
  cfe830dc
- ARM sched model: Add integer VFP/SIMD instructions on Swift · eac54473
  Arnold Schwaighofer authored 11 years ago
```
Reapply 183269.

llvm-svn: 183441
```
  eac54473
- ARM sched model: Add integer load/store instructions on Swift · dff8e4c4
  Arnold Schwaighofer authored 11 years ago
```
Reapply 183268.

llvm-svn: 183438
```
  dff8e4c4
- ARM sched model: Add integer arithmetic instructions on Swift · 41a7b068
  Arnold Schwaighofer authored 11 years ago
```
Reapply 183267.

llvm-svn: 183436
```
  41a7b068
- ARM sched model: Cortex A9 - More InstRW sched resources · 57142859
  Arnold Schwaighofer authored 11 years ago
```
Add more InstRW mappings.

Reapply 183266.

llvm-svn: 183435
```
  57142859
- ARM sched model: Add branch thumb instructions · f1395b69
  Arnold Schwaighofer authored 11 years ago
```
Reapply 183265.

llvm-svn: 183432
```
  f1395b69
- ARM sched model: Add branch thumb2 instructions · 10ccc99c
  Arnold Schwaighofer authored 11 years ago
```
Reapply 183264.

llvm-svn: 183430
```
  10ccc99c
- ARM sched model: Add branch instructions · 91d4ee37
  Arnold Schwaighofer authored 11 years ago
```
Reapply 183263.

llvm-svn: 183428
```
  91d4ee37
- ARM sched model: Add preload thumb2 instructions · 57727977
  Arnold Schwaighofer authored 11 years ago
```
Reapply 183262.

llvm-svn: 183427
```
  57727977
- ARM sched model: Add preload instructions · 1b413304
  Arnold Schwaighofer authored 11 years ago
```
Reapply 183261.

llvm-svn: 183425
```
  1b413304
- ARM sched model: Add more ALU and CMP thumb instructions · 654649dd
  Arnold Schwaighofer authored 11 years ago
```
Reapply of 183260.

llvm-svn: 183423
```
  654649dd
- ARM sched model: Add more ALU and CMP thumb2 instructions · 972ce477
  Arnold Schwaighofer authored 11 years ago
```
Reapply of 183259.

llvm-svn: 183421
```
  972ce477
- R600: Remove leftover code in R600MachineScheduler.cpp · 54476a15
  Vincent Lejeune authored 11 years ago
```
Spotted by Benjamin Kramer.

llvm-svn: 183413
```
  54476a15
- Cast to the correct type. Pointer, not reference. · b9121681
  Bill Wendling authored 11 years ago
```
llvm-svn: 183385
```
  b9121681
- R600OptimizeVectorRegisters.cpp: Tweak a warning. [-Wsometimes-uninitialized] · 4a8f0793
  NAKAMURA Takumi authored 11 years ago
```
FIXME: Is it false alarm?
llvm-svn: 183371
```
  4a8f0793
- R600OptimizeVectorRegisters.cpp: Suppress a warning. [-Wunused-variable] · e5555fc2
  NAKAMURA Takumi authored 11 years ago
```
llvm-svn: 183370
```
  e5555fc2
- Trailing linefeed. · 372574d4
  NAKAMURA Takumi authored 11 years ago
```
llvm-svn: 183369
```
  372574d4
- Cast to the proper type. · e4105768
  Bill Wendling authored 11 years ago
```
llvm-svn: 183365
```
  e4105768
- Cache the TargetLowering info object as a pointer. · f7719085
  Bill Wendling authored 11 years ago
```
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.

llvm-svn: 183361
```
  f7719085
- R600: Replace predicate loop with predicate function · acec99c9
  Tom Stellard authored 11 years ago
```
llvm-svn: 183351
```
  acec99c9
Jun 05, 2013

R600: Add a pass that merge Vector Register · dec18752

Vincent Lejeune authored 11 years ago

Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.

llvm-svn: 183343

dec18752

R600: Schedule copy from phys register at beginning of block · 4b5b8497
Vincent Lejeune authored 11 years ago
```
It allows regalloc pass to remove them by trivially assigning associated reg

llvm-svn: 183336
```
4b5b8497
[mips] brcond + setgt/setugt instruction selection patterns. · da4496c8
Akira Hatanaka authored 11 years ago
```
llvm-svn: 183334
```
da4496c8

[PATCH] Fix VGATHER* operand constraints · 00b20cc9

Michael Liao authored 11 years ago

Add earlyclobber constaints to prevent input register being allocated as
the output register because, according to Intel spec [1], "If any pair
of the index, mask, or destination registers are the same, this
instruction results a UD fault."

---
[1] http://software.intel.com/sites/default/files/319433-014.pdf

llvm-svn: 183327

00b20cc9