- Apr 12, 2013
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Benjamin Kramer authored
Fix a disconcerting bug in Value::isUsedInBasicBlock, which gave wrong answers for blocks larger than 3 instrs. Also add a unit test. PR15727. llvm-svn: 179370
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Alexey Samsonov authored
llvm-svn: 179367
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Nico Rieck authored
llvm-svn: 179363
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Nico Rieck authored
llvm-svn: 179362
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Nico Rieck authored
llvm-svn: 179361
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Nico Rieck authored
This test ensures that relocation type names returned by libObject match the raw relocation type value. llvm-svn: 179360
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Nico Rieck authored
This option expands shown relocations from single line to a dictionary format: Relocation { Offset: 0x4 Type: R_386_32 (1) Symbol: sym Info: 0x0 } llvm-svn: 179359
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Nico Rieck authored
llvm-svn: 179358
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Nico Rieck authored
MIPS64EL relocation entries have up to three relocation operations. Because libObject only exposes a single relocation name, use the concatenation of the individual relocation type names. llvm-svn: 179357
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Hal Finkel authored
This is prep. work for the implementation of optimizeCompare. Many PPC instructions have 'record' forms (in almost all cases, this means that the RC bit is set) that cause the result of the instruction to be compared with zero, and the result of that comparison saved in a predefined condition register. In order to add the record forms of the instructions without too much copy-and-paste, the relevant functions have been refactored into multiclasses which define both the record and normal forms. Also, two TableGen-generated mapping functions have been added which allow querying the instruction code for the record form given the normal form (and vice versa). No functionality change intended. llvm-svn: 179356
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Nadav Rotem authored
llvm-svn: 179355
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Nadav Rotem authored
llvm-svn: 179354
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Nadav Rotem authored
When debugging performance regressions we often ask ourselves if the regression that we see is due to poor isel/sched/ra or due to some micro-architetural problem. When comparing two code sequences one good way to rule out front-end bottlenecks (and other the issues) is to force code alignment. This pass adds a flag that forces the alignment of all of the basic blocks in the program. llvm-svn: 179353
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Rafael Espindola authored
Original message: Print more information about relocations. With this patch llvm-readobj now prints if a relocation is pcrel, its length, if it is extern and if it is scattered. It also refactors the code a bit to use bit fields instead of shifts and masks all over the place. llvm-svn: 179345
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Chad Rosier authored
variables that use namespace alias qualifiers. Test case coming on clang side shortly. Part of rdar://13499009 llvm-svn: 179343
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Chad Rosier authored
namespace alias qualifiers. Test case coming on clang side shortly. Part of rdar://13499009 llvm-svn: 179339
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Manman Ren authored
Added PathAliases to check if two struct-path tags can alias. Added command line option -struct-path-tbaa. llvm-svn: 179337
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Chad Rosier authored
can build up the identifier string. No test case as support for looking up these type of identifiers hasn't been implemented on the clang side. Part of rdar://13499009 llvm-svn: 179336
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Manman Ren authored
llvm-svn: 179331
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Chad Rosier authored
commit. Part of rdar://13453209 llvm-svn: 179325
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- Apr 11, 2013
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Chad Rosier authored
specific logic. This makes the code much less fragile. Test case coming on the clang side in a moment. rdar://13634327 llvm-svn: 179323
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Preston Gurd authored
llvm-svn: 179322
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David Majnemer authored
A64Imms::isLogicalImmBits and A64Imms::isLogicalImm will attempt to execute shifts that perform undefined behavior. Instead of attempting to perform the 64-bit rotation, treat it as a no-op. llvm-svn: 179317
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David Majnemer authored
Allows LLVM to optimize sequences like the following: %add = add nsw i32 %x, 1 %cmp = icmp sgt i32 %add, %y into: %cmp = icmp sge i32 %x, %y as well as: %add1 = add nsw i32 %x, 20 %add2 = add nsw i32 %y, 57 %cmp = icmp sge i32 %add1, %add2 into: %add = add nsw i32 %y, 37 %cmp = icmp sle i32 %cmp, %x llvm-svn: 179316
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Jack Carter authored
These changes are based on commit responses for r179135. llvm-svn: 179315
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Akira Hatanaka authored
multiply instructions in MipsSEDAGToDAGISel. This patch was supposed to be part of r178403. llvm-svn: 179314
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Akira Hatanaka authored
- Rename function. - Pass iterator by value. - Remove header include. No functionality changes. llvm-svn: 179312
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Rafael Espindola authored
llvm-svn: 179303
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Rafael Espindola authored
llvm-svn: 179298
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Rafael Espindola authored
With this patch llvm-readobj now prints if a relocation is pcrel, its length, if it is extern and if it is scattered. It also refactors the code a bit to use bit fields instead of shifts and masks all over the place. llvm-svn: 179294
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Benjamin Kramer authored
When trying to collapse sequences of insertelement/extractelement instructions into single shuffle instructions, there is one specific case where the Instruction Combiner wrongly updates the resulting Mask of shuffle indexes. The problem is in function CollectShuffleElments. If we have a sequence of insert/extract element instructions like the one below: %tmp1 = extractelement <4 x float> %LHS, i32 0 %tmp2 = insertelement <4 x float> %RHS, float %tmp1, i32 1 %tmp3 = extractelement <4 x float> %RHS, i32 2 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 3 Where: . %RHS will have a mask of [4,5,6,7] . %LHS will have a mask of [0,1,2,3] The Mask of shuffle indexes is wrongly computed to [4,1,6,7] instead of [4,0,6,7]. When analyzing %tmp2 in order to compute the Mask for the resulting shuffle instruction, the algorithm forgets to update the mask index at position 1 with the index associated to the element extracted from %LHS by instruction %tmp1. Patch by Andrea DiBiagio! llvm-svn: 179291
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Eli Bendersky authored
Thanks to Reid Kleckner for catching this. llvm-svn: 179289
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Rafael Espindola authored
This will be used in clang to decide if it should create an @file or not. It will be tested on the clang side. Patch by Nathan Froyd. llvm-svn: 179285
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Alexey Samsonov authored
llvm-svn: 179280
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Sylvestre Ledru authored
llvm-svn: 179279
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Benjamin Kramer authored
llvm-svn: 179277
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Benjamin Kramer authored
llvm-svn: 179276
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Benjamin Kramer authored
llvm-svn: 179275
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Benjamin Kramer authored
Rename the C function to create a SLPVectorizerPass to something sane and expose it in the header file. llvm-svn: 179272
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Michael Liao authored
As packed comparisons in AVX/SSE produce all 0s or all 1s in each SIMD lane, vector select could be simplified to AND/OR or removed if one or both values being selected is all 0s or all 1s. llvm-svn: 179267
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