llvm-svn: 123145

llvm-svn: 123144

llvm-svn: 123143

llvm-svn: 123142

llvm-svn: 123141

Fix the TargetRegisterInfo::NoRegister places where someone preferred
typing 'TargetRegisterInfo::NoRegister' instead of typing '0'.

Note that TableGen is already emitting xx::NoRegister in xxGenRegisterNames.inc.

llvm-svn: 123140

llvm-svn: 123139

NUW AddRec's much more aggressively.  We now get a trip count
for @test2 in nsw.ll

llvm-svn: 123138

The numbering plan is now:

0           NoRegister.
[1;2^30)    Physical registers.
[2^30;2^31) Stack slots.
[2^31;2^32) Virtual registers. (With -1u and -2u used by DenseMapInfo.)

Each segment is filled from the left, so any mistaken interpretation should
quickly cause crashes.

FirstVirtualRegister has been removed. TargetRegisterInfo provides predicates
conversion functions that should be used instead of interpreting register
numbers manually.

It is now legal to pass NoRegister to isPhysicalRegister() and
isVirtualRegister(). The result is false in both cases.

It is quite rare to represent stack slots in this way, so isPhysicalRegister()
and isVirtualRegister() require that isStackSlot() be checked first if it can
possibly return true. This allows a very fast implementation of the common
predicates.

llvm-svn: 123137

llvm-svn: 123136

perform rounding other than truncation in the IR. Common C code for this
turns into really an LLVM intrinsic call that blocks a lot of further
optimizations.

llvm-svn: 123135

a + {b,+,stride} into {a+b,+,stride}  (because a is LIV),
then the resultant AddRec is NUW/NSW if the client says it
is.

llvm-svn: 123133

void f(int* begin, int* end) { std::fill(begin, end, 0); }

which turns into a != exit expression where one pointer is
strided and (thanks to step #1) known to not overflow, and 
the other is loop invariant.

The observation here is that, though the IV is strided by
4 in this case, that the IV *has* to become equal to the
end value.  It cannot "miss" the end value by stepping over
it, because if it did, the strided IV expression would
eventually wrap around.

Handle this by turning A != B into "A-B != 0" where the A-B
part is known to be NUW.

llvm-svn: 123131

when no virtual registers have been allocated.

It was only used to resize IndexedMaps, so provide an IndexedMap::resize()
method such that

 Map.grow(MRI.getLastVirtReg());

can be replaced with the simpler

 Map.resize(MRI.getNumVirtRegs());

This works correctly when no virtuals are allocated, and it bypasses the to/from
index conversions.

llvm-svn: 123130

llvm-svn: 123129

physical register numbers.

This makes the hack used in LiveInterval official, and lets LiveInterval be
oblivious of stack slots.

The isPhysicalRegister() and isVirtualRegister() predicates don't know about
this, so when a variable may contain a stack slot, isStackSlot() should always
be tested first.

llvm-svn: 123128

llvm-svn: 123126

llvm-svn: 123125

without informing memdep.  This could cause nondeterminstic weirdness 
based on where instructions happen to get allocated, and will hopefully
breath some life into some broken testers.

llvm-svn: 123124

llvm-svn: 123123

llvm-svn: 123122

llvm-svn: 123121

llvm-svn: 123120

config.h was generated, so it had no effect on it.

Thanks to arrowdodger for pointing out this and a tentative patch.

llvm-svn: 123119

llvm-svn: 123117

llvm-svn: 123116

llvm-svn: 123115

llvm-svn: 123114

Also, switch to a more clear 'sink' function with its declaration to
avoid any confusion about 'g'. Thanks for the suggestion Frits.

llvm-svn: 123113

llvm-svn: 123112

llvm-svn: 123111

of using a Location class with the same information.

When making a copy of a MachineOperand that was already stored in a
MachineInstr, it is necessary to clear the parent pointer on the copy. Otherwise
the register use-def lists become inconsistent.

Add MachineOperand::clearParent() to do that. An alternative would be a custom
MachineOperand copy constructor that cleared ParentMI. I didn't want to do that
because of the performance impact.

llvm-svn: 123109

llvm-svn: 123108

Print virtual registers numbered from 0 instead of the arbitrary
FirstVirtualRegister. The first virtual register is printed as %vreg0.
TRI::NoRegister is printed as %noreg.

llvm-svn: 123107

llvm-svn: 123106

with GEP instructions are always NUW, because PHIs cannot wrap
the end of the address space.

llvm-svn: 123105

that have the bit set.

llvm-svn: 123104

llvm-svn: 123103

llvm-svn: 123102

depending on TRI::FirstVirtualRegister.

Also use TRI::printReg instead of printing virtual registers directly.

llvm-svn: 123101