Prefix IR dumps with LiveInterval indices when possible.  This turns
this:

	%ESI<def> = MOV32rr %EDI<kill>
	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	%reg1027<def> = MOVZX64rr32 %ESI
	%reg1027<def> = ADD64ri8 %reg1027, 15, %EFLAGS<imp-def,dead>
	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
	%RDI<def> = MOV64rr %RSP
	%RDI<def> = SUB64rr %RDI, %reg1027<kill>, %EFLAGS<imp-def,dead>
	%RSP<def> = MOV64rr %RDI

into this:

4	%reg1024<def> = MOV32rr %EDI<kill>
12	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
20	%reg1025<def> = MOVZX64rr32 %reg1024
28	%reg1026<def> = MOV64rr %reg1025<kill>
36	%reg1026<def> = ADD64ri8 %reg1026, 15, %EFLAGS<imp-def,dead>
44	%reg1027<def> = MOV64rr %reg1026<kill>
52	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
60	%reg1028<def> = MOV64rr %RSP
68	%reg1029<def> = MOV64rr %reg1028<kill>
76	%reg1029<def> = SUB64rr %reg1029, %reg1027<kill>, %EFLAGS<imp-def,dead>
84	%RSP<def> = MOV64rr %reg1029

This helps greatly when debugging register allocation and coalescing
problems.

llvm-svn: 76615

llvm-svn: 76614

llvm-svn: 76613

llvm-svn: 76612

llvm-svn: 76611

llvm-svn: 76610

llvm-svn: 76609

llvm-svn: 76608

llvm-svn: 76607

llvm-svn: 76606

functions that return a value.  I was going to buffer the whole lot
up, but it should be easier to review if I check them in
incrementally.  Most of the forth coming changes either add a return
value, or make it impossible to return, or alter the return type.

llvm-svn: 76605

and call PrintGlobalVariable, allowing elimination and simplification
of various targets.

llvm-svn: 76604

Add PrefixPrinter arguments to the dump routines for MachineFunction and
MachineBasicBlock.  We'll use these shortly.

llvm-svn: 76603

Add a small utility class to configure IR printers.  This will allow
printers to do neat and wonderful things when printing debug
information.  The ideas is to allow passes to configer printers to emit
pass-specific information when dumping IR.

llvm-svn: 76602

Make a bunch of changes suggested by Chris and others to improve
efficiency.  Fix a few formatting bugs along the way.

llvm-svn: 76601

llvm-svn: 76600

llvm-svn: 76599

llvm-svn: 76598

llvm-svn: 76597

llvm-svn: 76596

llvm-svn: 76595

llvm-svn: 76594

chain to the super class instead of initializing mangler directly.
This gives it .file and module level inline asm support among other
things.

llvm-svn: 76593

This eliminates redundancy setting up the mangler and adds support to them
for module-level inline asm and a .file directive.

llvm-svn: 76592

llvm-svn: 76591

LLVM IR concept.

llvm-svn: 76590

Also, tweak the return type of size().

llvm-svn: 76588

llvm-svn: 76587

llvm-svn: 76586

vectors needlessly, doxygenify comments, improve constness, etc.

llvm-svn: 76585

llvm-svn: 76583

llvm-svn: 76579

as much, etc.

llvm-svn: 76578

llvm-svn: 76577

Zaffanella, with tweaks from Abramo Bagnara.

llvm-svn: 76576

llvm-svn: 76559

Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past.

llvm-svn: 76558

llvm-svn: 76555

llvm-svn: 76554

llvm-svn: 76553