llvm-svn: 14588

llvm-svn: 14587

llvm-svn: 14585

llvm-svn: 14584

llvm-svn: 14581

llvm-svn: 14570

don't exist, we don't have to pretend to handle them.

llvm-svn: 14567

Also, while noone's looking, add support for constant expressions.  Wait,
I said not to look!

llvm-svn: 14566

llvm-svn: 14565

llvm-svn: 14564

pass is required to paper over problems in the code generator (primarily
live variables and its clients) which doesn't really have any well defined
semantics for unreachable code.

The proper solution to this problem is to have instruction selectors not
select blocks that are unreachable.  Until we have a instruction selection
framework available for use, however, we can't expect all instruction
selector writers to do this.  Until then, this pass should be used.

llvm-svn: 14563

llvm-svn: 14560

Also, the RETURN instructions are not used in the sparcv9 backend.

llvm-svn: 14559

When in doubt, stamp it out!!

llvm-svn: 14558

* Also leave space for spilling integer registers (this should be calculated)

llvm-svn: 14554

* Use the SetCC handling code in the format of Brian's V8
* Add FIXMEs where calls to functions are being made without adding them to the
  Module first... they cause missing symbols at assembly-time.

llvm-svn: 14553

llvm-svn: 14552

* Do not define CR register class because we don't (yet) have the i4 type

llvm-svn: 14551

llvm-svn: 14550

Contributed by Vladimir Merzliakov!

llvm-svn: 14546

llvm-svn: 14541

Contributed by Vladimir Prus!

llvm-svn: 14534

any other data structures

llvm-svn: 14524

use them instead of a local LiveVariables numbering

llvm-svn: 14523

mapping

llvm-svn: 14521

llvm-svn: 14520

map.

llvm-svn: 14518

Also convert df_iterator -> df_ext_iterator for subsequent stuff I'm doing.

llvm-svn: 14517

llvm-svn: 14512

* Congregate more branch-and-link opcodes together
* Mark FP, CPR, and special registers as volatile across calls

llvm-svn: 14511

* Define the condition register class

llvm-svn: 14510

* Only check for a register if we are sure the instruction has one allocated

llvm-svn: 14509

llvm-svn: 14508

the PC in a code sequence for global variables.

llvm-svn: 14506

  for the function
* Registers aren't necessarily sequential wrt their enums, don't rely on it
  when emitting function arguments into sequential registers
* Remove X86-specific comments about AL/BL/AH/BH/EDX/etc
* Add an abort() for an unimplemented signed right shift
* The src operand for a GEP was never emitted!  Fixed.
* We can skip zero-valued GEP indices as they are no-ops.

"Hello, World!" now works.

llvm-svn: 14505

* Only increment labelNumber once, because it's used by both Load{hi,lo}Addr
* There is no .bss section on PowerPC
* Use .align 2 instead of other random numbers

llvm-svn: 14504

llvm-svn: 14502

* Specify the isCall bit and caller-save registers for some call instrs

llvm-svn: 14501

llvm-svn: 14500

llvm-svn: 14497