merging x >u 5 and x <s 20 because it's impossible to implement.

llvm-svn: 91228

llvm-svn: 91223

No testcase yet - it seems we're exposing generic codegen bugs.

llvm-svn: 91221

llvm-svn: 91220

llvm-svn: 91219

just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.

llvm-svn: 91200

Based on the patch by Brian Lucas!

llvm-svn: 91175

llvm-svn: 91158

memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around.

llvm-svn: 91150

This is used in some weird cases like general dynamic TLS model.
This fixes PR5723

llvm-svn: 91144

llvm-svn: 91143

llvm-svn: 91140

llvm-svn: 91104

llvm-svn: 91090

llvm-svn: 91053

Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.

llvm-svn: 91003

vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>

iff ptr is 16-byte aligned (or can be made into 16-byte aligned).

llvm-svn: 90984

llvm-svn: 90925

Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's primary used by selectdag passes.

llvm-svn: 90922

- Also support the 'q' NEON registers asm code.

llvm-svn: 90894

Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra instruction. Patch inspired by Brian Lucas!

llvm-svn: 90819

current form, it is too expensive in compile time.

llvm-svn: 90781

llvm-svn: 90742

llvm-svn: 90740

llvm-svn: 90739

llvm-svn: 90737

in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4

llvm-svn: 90724

llvm-svn: 90656

- Privatize a typedef.
- Call the InvalidateEntry when refining a type.

llvm-svn: 90655

llvm-svn: 90640

llvm-svn: 90639

MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.

llvm-svn: 90634

Remove an unneeded include.

llvm-svn: 90625

Have hasLoad/StoreFrom/ToStackSlot return the relevant MachineMemOperand.

llvm-svn: 90608

llvm-svn: 90588

llvm-svn: 90490

llvm-svn: 90429

llvm-svn: 90428

llvm-svn: 90419

both source operands.  In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand.  Radar 7434842.

llvm-svn: 90417