SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.

llvm-svn: 46659

llvm-svn: 46623

Add an extra operand to LABEL nodes which distinguishes between debug, EH, or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution.

llvm-svn: 46609

Allow ComplexExpressions in InstrInfo.td files to be slightly more... complex! ComplexExpressions can now have attributes which affect how TableGen interprets
the pattern when generating matchin code. 

The first (and currently, only) attribute causes the immediate parent node of the ComplexPattern operand to be passed into the matching code rather than the node at the root of the entire DAG containing the pattern.

llvm-svn: 46606

in the backend. Introduce a new SDNode type, MemOperandSDNode, for
holding a MemOperand in the SelectionDAG IR, and add a MemOperand
list to MachineInstr, and code to manage them. Remove the offset
field from SrcValueSDNode; uses of SrcValueSDNode that were using
it are all all using MemOperandSDNode now.

Also, begin updating some getLoad and getStore calls to use the
PseudoSourceValue objects.

Most of this was written by Florian Brander, some
reorganization and updating to TOT by me.

llvm-svn: 46585

llvm-svn: 46563

llvm-svn: 46512

generated. This feature would only show up in fairly complex patterns, such
as this one in CellSPU:

  def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)),
	    (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;

which generated the following emit code:

SDNode *Emit_0(const SDOperand &N, unsigned Opc0, unsigned Opc1, MVT::ValueType VT0, MVT::ValueType VT1) DISABLE_INLINE {
  SDOperand N0 = N.getOperand(0);
  SDOperand N00 = N0.getOperand(0);
  SDOperand N01 = N0.getOperand(1);
  SDOperand N1 = N.getOperand(1);
  SDOperand N10 = N1.getOperand(0);
  SDOperand N11 = N1.getOperand(1);
  SDOperand Tmp3(CurDAG->getTargetNode(Opc0, VT0, N00), 0);
  return CurDAG->SelectNodeTo(N.Val, Opc1, VT1, Tmp3, Tmp2); /* Tmp2 s/b N00 */
}

Tested against the test suites without incident.

llvm-svn: 46487

llvm-svn: 46250

llvm-svn: 46223

llvm-svn: 46180

llvm-svn: 46112

Add files to windows project files.  Also include <algorithm> explicitly so that vstudio build works

llvm-svn: 46013

Rename CCIfStruct to CCIfByVal and CCStructAssign to CCPassByVal. Remove unused parameters of CCStructAssign and add size and alignment requirement info.

llvm-svn: 45997

llvm-svn: 45994

llvm-svn: 45964

llvm-svn: 45900

ByVal arguments are passed on stack. Make sure to allocate a slot using size and alignment information on the parameter attribute.

llvm-svn: 45897

both work right according to the new flags.

This removes the TII::isReallySideEffectFree predicate, and adds
TII::isInvariantLoad. 

It removes NeverHasSideEffects+MayHaveSideEffects and adds
UnmodeledSideEffects as machine instr flags.  Now the clients
can decide everything they need.

I think isRematerializable can be implemented in terms of the
flags we have now, though I will let others tackle that.

llvm-svn: 45843

x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects.  It would be really nice if we could
write patterns for copy instructions.

I have audited all the x86 instructions down to MOVDQAmr.  The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.

llvm-svn: 45829

llvm-svn: 45827

llvm-svn: 45823

llvm-svn: 45822

llvm-svn: 45819

Also, instructions with any nodes that are SDNPMayLoad also read memory.

llvm-svn: 45817

This is currently not set by anything.

llvm-svn: 45748

Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695

all clients over to using predicates instead of these flags directly.
These are now private values which are only to be used to statically
initialize the tables.

llvm-svn: 45692

Evan, please review the comments I added to getNumDefs to make sure
that they are accurate, thx.

llvm-svn: 45687

TargetInstrDescriptor class and shrink to 16-bits, saving a 
word in TargetInstrDescriptor.  Add some comments.

llvm-svn: 45686

just unconditionally use the def name of the instruction.

llvm-svn: 45684

over to using them, instead of diddling Flags directly.  Change the
various flags from const variables to enums.

llvm-svn: 45677

llvm-svn: 45667

llvm-svn: 45656

instead of "ISD::STORE".  This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores).  This allows us to remove
more explicit isStore flags from the .td files.

Finally, add a warning for when a .td file contains an explicit 
isStore and tblgen is able to infer it.

llvm-svn: 45654

intrinsic that writes to memory.

llvm-svn: 45650

occured in a pattern, but failed miserably.  The new code works for
any instruction that has a store in its pattern, including all the 
x86 mem op mem instructions.

The only target-independent code that uses this is branch folding,
so this won't change anything in practice.

llvm-svn: 45648

rearrange some code to allow inferring instr info from the pattern of the instr, but don't do so yet.

llvm-svn: 45647

llvm-svn: 45646

llvm-svn: 45645