- Due to the current matching vector elements constraints in ISD::FP_EXTEND,
  rounding from v2f32 to v2f64 is scalarized. Add a customized v2f32 widening
  to convert it into a target-specific X86ISD::VFPEXT to work around this
  constraints. This patch also reverts a previous attempt to fix this issue by
  recovering the scalarized ISD::FP_EXTEND pattern and thus significantly
  reduces the overhead of supporting non-power-2 vector FP extend.

llvm-svn: 165625

constructor with invalid code.

rdar://12240916

llvm-svn: 165623

llvm-svn: 165621

LLVM_EXTERNAL_CLANG_TOOLS_EXTRA_SOURCE_DIR=/path/to/llvm-srcroot/tools/clang/tools/extra, by default.

llvm-svn: 165620

FIXME: Would you like to run llvm/unittests w/o LLVM_BUILD_TESTS regardless of LLVM_BUILD_TOOLS?
llvm-svn: 165619

llvm-svn: 165618

SDNode for LDRB_POST_IMM is invalid: number of registers added to SDNode fewer
that described in .td.

7 ops is needed, but SDNode with only 6 is created.

In more details:
In ARMInstrInfo.td, in multiclass AI2_ldridx, in definition _POST_IMM, offset
operand is defined as am2offset_imm. am2offset_imm is complex parameter type,
and actually it consists from dummy register and imm itself. As I understood
trick with dummy reg was made for AsmParser. In ARMISelLowering.cpp, this dummy
register was not added to SDNode, and it cause crash in Peephole Optimizer pass.

The problem fixed by setting up additional dummy reg when emitting
LDRB_POST_IMM instruction.

llvm-svn: 165617

SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack
objects and byval parameters. So loading byval parameters from stack may be
inserted *before* it will be stored, since these operations are treated as
independent.

Fix:
Currently ARMTargetLowering::LowerFormalArguments saves byval registers with
FixedStack MachinePointerInfo. To fix the problem we need to store byval
registers with MachinePointerInfo referenced to first the "byval" parameter.

Also commit adds two new fields to the InputArg structure: Function's argument
index and InputArg's part offset in bytes relative to the start position of
Function's argument. E.g.: If function's argument is 128 bit width and it was
splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index,
but different offset values. 

llvm-svn: 165616

The issue arises when coercing to/from types of different sizes. We need
to be certain that the allocation on either end has sufficient room for
the coerced type. When it doesn't, we need to make room, copy across,
and then proceed. PR11905 handled the case of storing function arguments
back into allocas in the function prolog, this patch handles the case of
setting up the function arguments in a call expression.

This is actually significantly simpler than the fix for PR11905. It ends
up being a trivial change to create a temporary alloca when the source
is too small and memcpy across. This should preserve the compile-time
fast-isel benefits of doing gep+load sequences and avoiding FCAs.

Reviewed by Benjamin and Evgeniy (who fixed PR11905).

llvm-svn: 165615

llvm-svn: 165613

namespace. Use the attribute's enum value instead. No functionality change
intended.

llvm-svn: 165611

namespace. Use the attribute's enum value instead. No functionality change
intended.

llvm-svn: 165610

AAPCS ABI Section 7.1.4 [1] specifies that va_list
should be defined as struct __va_list { void *__ap;};
And in C++, it is defined in namespace std.

[1] http://infocenter.arm.com/help/topic
         /com.arm.doc.ihi0042d/IHI0042D_aapcs.pdf

Patch by Weiming Zhao.

llvm-svn: 165609

checkRegMaskInterference only initializes the bitmask on the first interference.

This fixes PR14027 and (re)fixes PR13945.

llvm-svn: 165608

enums. These are then created via the correct Attributes creation method.

llvm-svn: 165607

llvm-svn: 165606

llvm-svn: 165605

Consistently evaluate Aliases and Sequences recursively.

llvm-svn: 165604

Allows the new machine model to be used for NumMicroOps and OutputLatency.

Allows the HazardRecognizer to be disabled along with itineraries.

llvm-svn: 165603

llvm-svn: 165602

llvm-svn: 165601

llvm-svn: 165600

llvm-svn: 165599

llvm-svn: 165597

Have 'addFnAttr' take the attribute enum value. Then have it build the attribute object and add it appropriately. No functionality change.

llvm-svn: 165596

Have 'addFnAttr' take the attribute enum value. Then have it build the attribute object and add it appropriately. No functionality change.

llvm-svn: 165595

llvm-svn: 165594

and modules are not enabled.

llvm-svn: 165593

an invalid location if the location points to the synthetic buffer
for the module input.

llvm-svn: 165592

This means the main file for modules will always be a virtual one.

llvm-svn: 165591

llvm-svn: 165590

Patch committed on behalf of Kirill Uhanov

llvm-svn: 165589

llvm-svn: 165588

API (to get the length of x86 instructions) to using the LLVM-MC
disassembler.
<rdar://problem/12411000>

llvm-svn: 165587

This patch adds new functions to the SectionRef and ObjectFile interfaces to determine whether or not a section is meant to be read-only.  These functions will be used by the MCJIT RuntimeDyld to give hints to the memory manager during the object loading process in a future patch.

Patch by Ashok Thirumurthi.

llvm-svn: 165586

Patch by Sasa Stankovic. 

llvm-svn: 165585

llvm-svn: 165584

llvm-svn: 165583

llvm-svn: 165582

llvm-svn: 165581