specified.  The various *imm operands defined by PPC are really all i32,
even though the actual immediate is restricted to a smaller value in it.

llvm-svn: 23352

llvm-svn: 23350

llvm-svn: 23347

llvm-svn: 23342

can use/define class methods

llvm-svn: 23339

with incoming arguments instead of the pregs themselves.  This fixes
the scheduler from causing problems by moving a copyfromreg for an argument
to after a select_cc node (now it can, and bad things won't happen).

llvm-svn: 23334

llvm-svn: 23333

llvm-svn: 23332

llvm-svn: 23330

llvm-svn: 23329

llvm-svn: 23304

for FP as well.  This triggers a couple dozen times on 177.mesa (for example).

llvm-svn: 23299

with copies, leading to code like this:

       lwz r4, 380(r1)
       or r10, r4, r4    ;; Last use of r4

By teaching the PPC backend how to fold spills into copies, we now get this
code:

       lwz r10, 380(r1)

wow. :)

This reduces a testcase nate sent me from 1505 instructions to 1484.

Note that this could handle FP values but doesn't currently, for reasons
mentioned in the patch

llvm-svn: 23298

llvm-svn: 23297

is zero.  This lets the register allocator elide some copies in some cases.

This implements CodeGen/PowerPC/rlwimi-commute.ll

llvm-svn: 23292

1. Add support for defining Pattern's, which can match expressions when there
   is no instruction that directly implements something.  Instructions usually
   implicitly define patterns.
2. Add support for defining SDNodeXForm's, which are node transformations.
   This seperates the concept of a node xform out from the existing predicate
   support.

Using this new stuff, we add a few instruction patterns, one for testing, and
two for OR/XOR by an arbitrary immediate.

llvm-svn: 23286

llvm-svn: 23283

the rest of the instructions, add comment markers to seperate portions of
the file into logical parts

llvm-svn: 23277

llvm-svn: 23268

for matching signed 16-bit and shifted 16-bit ppc immediates

llvm-svn: 23267

llvm-svn: 23266

llvm-svn: 23263

llvm-svn: 23262

'' is not a recognized processor for this target (ignoring processor)

Default to "generic" instead of "" for the default CPU.

llvm-svn: 23257

'' is not a recognized processor for this target (ignoring processor)

instead of:

 is not a recognized processor for this target (ignoring processor)

llvm-svn: 23256

are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts,
such as the PowerPC 970.

This speeds up 189.lucas from 81.99 to 32.64 seconds.

llvm-svn: 23250

llvm-svn: 23246

llvm-svn: 23245

generate the fun in-register fp<->long instructions.

llvm-svn: 23244

llvm-svn: 23241

llvm-svn: 23240

llvm-svn: 23239

llvm-svn: 23238

switch should never be exited, so its bottom is now unreachable.

llvm-svn: 23234

Define the PatFrag class which can be used to define subpatterns to match
things with.  Define 'not', and use it to define the patterns for andc,
nand, etc.

llvm-svn: 23233

llvm-svn: 23232

currently don't do anything.  This elides patterns for binary operators
that ping on the carry flag, since we don't model it yet.

This patch also removes PPC::SUB, because it is dead.

llvm-svn: 23230

llvm-svn: 23226

llvm-svn: 23222

llvm-svn: 23220