* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.

llvm-svn: 24587

  chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
  chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.

llvm-svn: 24586

llvm-svn: 24585

llvm-svn: 24584

llvm-svn: 24583

llvm-svn: 24582

llvm-svn: 24581

llvm-svn: 24580

llvm-svn: 24579

This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc
turned on.  Given a clean nightly tester run, we should be able to turn it
on by default!

llvm-svn: 24578

llvm-svn: 24577

from .bc files.

llvm-svn: 24575

llvm-svn: 24574

llvm-svn: 24573

llvm-svn: 24572

should come from the arbitrary ops map.

This fixes Regression/CodeGen/PowerPC/2005-12-01-Crash.ll

llvm-svn: 24571

llvm-svn: 24570

Attempting to run it will find lli's main, which isn't the desired effect.

llvm-svn: 24569

llvm-svn: 24568

stuff isn't using ISelLowering.cpp

llvm-svn: 24567

llvm-svn: 24566

selecting a node and use a mix of getTargetNode() and SelectNodeTo.  Because
SelectNodeTo didn't check the CSE maps for a preexisting node and didn't insert
its result into the CSE maps, we would sometimes miss a CSE opportunity.

This is extremely rare, but worth fixing for completeness.

llvm-svn: 24565

llvm-svn: 24564

work.  This change has no effect on generated code.

llvm-svn: 24563

llvm-svn: 24562

llvm-svn: 24561

llvm-svn: 24560

llvm-svn: 24559

llvm-svn: 24558

def SHL8rCL  : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
                 "shl{b} {%cl, $dst|$dst, %CL}",
                 [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;

This generates a CopyToReg operand and added its 2nd result to the shl as
a flag operand.

llvm-svn: 24557

llvm-svn: 24556

ValueType from the RegisterClass or Operands.  This step is necessary to
allow RegisterClasses to have multiple ValueTypes.

llvm-svn: 24555

llvm-svn: 24554

permit future changes.

llvm-svn: 24553

llvm-svn: 24552

llvm-svn: 24551

llvm-svn: 24550

llvm-svn: 24549

llvm-svn: 24548

llvm-svn: 24547