llvm-svn: 113847

llvm-svn: 113846

by morphing the 'and' to its recording form 'andS'.

This is basically a test commit into this area, to
see whether the bots like me. Several generalizations
can be applied and various avenues of code simplification
are open. I'll introduce those as I go.

I am aware of stylistic input from Bill Wendling, about
where put the analysis complexity, but I am positive
that we can move things around easily and will find a
satisfactory solution.

llvm-svn: 113839

llvm-svn: 113837

This reverts commit r113632

Conflicts:

	cmake/modules/AddLLVM.cmake

llvm-svn: 113819

register allocation.  Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!

llvm-svn: 113818

pseudo-instruction approach.  Change ARMExpandPseudoInsts to use a table
to record all the NEON load/store information.

llvm-svn: 113812

llvm-svn: 113768

the end of the line on a parser error, allowing skipping to happen
for syntactic errors but not for semantic errors.  Before we would
miss emitting a diagnostic about the second line, because we skipped
it due to the semantic error on the first line:

  foo %eax
  bar %al

This fixes rdar://8414033 - llvm-mc ignores lines after an invalid instruction mnemonic errors

llvm-svn: 113688

llvm-svn: 113670

llvm-svn: 113666

the 'zero' bit down into the back-end. There are other cases where this logic
isn't sufficient, so they should be handled separately.

llvm-svn: 113665

llvm-svn: 113662

llvm-svn: 113659

llvm-svn: 113654

used for fast-isel.

llvm-svn: 113652

iterator when an optimization took place. This allows us to do more insane
things with the code than just remove an instruction or two.

llvm-svn: 113640

llvm-svn: 113637

llvm-svn: 113632

fixed operands from the total number of operands (including the variadic ones).

llvm-svn: 113597

llvm-svn: 113584

to use AddrMode4, there was a count of the registers stored in one of the
operands.  I changed that to just count the operands but forgot to adjust for
the size of D registers.  This was noticed by Evan as a performance problem
but it is a potential correctness bug as well, since it is possible that this
could merge a base update with a non-matching immediate.

llvm-svn: 113576

take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.

llvm-svn: 113570

llvm-svn: 113566

more clear.  No functional change.

llvm-svn: 113565

bad as I'd thought.

llvm-svn: 113561

some data around and implement a couple of move routines to do this.

llvm-svn: 113546

llvm-svn: 113537

Truncate when truncating, extend when extending.

llvm-svn: 113536

llvm-svn: 113533

llvm-svn: 113523

instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.

llvm-svn: 113513

the VST pseudos.  The VLD/VST scheduling still needs work (see pr6722), but
at least we shouldn't confuse the loads with the stores.

llvm-svn: 113473

llvm-svn: 113463

llvm-svn: 113461

llvm-svn: 113459

operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.

llvm-svn: 113456

llvm-svn: 113455

for integer and fp constants. Implement todo to use vfp3 instructions
to materialize easy constants if we can.

llvm-svn: 113453

For VLD3/VLD4 with double-spaced registers, add the implicit use of the
super register for both the instruction loading the even registers and the
instruction loading the odd registers.

llvm-svn: 113452