llvm-svn: 54518

llvm-svn: 54458

is X86 ATT only.

llvm-svn: 53355

llvm-svn: 53333

llvm-svn: 53319

llvm-svn: 53318

llvm-svn: 53316

llvm-svn: 53309

llvm-svn: 53280

This is a question of the debugging setup code not
being called at the right time, and it's called from
target-dependent code for some reason.  I have only
attempted to fix Darwin, but I'm pretty sure it's
broken elsewhere; I'll leave that to people who can
test it.

llvm-svn: 53254

llvm-svn: 53237

llvm-svn: 53215

ATT asm printer just print register AsmName's instead of calling tolower on each charater of Name. This speeds it up by 10%.

llvm-svn: 53208

the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.

llvm-svn: 52943

llvm-svn: 52929

llvm-svn: 52866

llvm-svn: 52865

llvm-svn: 52864

llvm-svn: 52863

llvm-svn: 52862

llvm-svn: 52861

llvm-svn: 52860

llvm-svn: 52859

llvm-svn: 52139

and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).

llvm-svn: 52044

$non_lazy_ptr's and $lazy_ptr's.

llvm-svn: 51277

are represented as "weak", but there are subtle differences
in some cases on Darwin, so we need both.  The intent
is that "common" will behave identically to "weak" unless
somebody changes their target to do something else.
No functional change as yet.

llvm-svn: 51118

but should work. Work is in progress, more models will follow

llvm-svn: 50630

correctly when unwind info is being generated.

llvm-svn: 49366

review feedback.
-enable-eh is still accepted but doesn't do anything.
EH intrinsics use Dwarf EH if the target supports that,
and are handled by LowerInvoke otherwise.
The separation of the EH table and frame move data is,
I think, logically figured out, but either one still
causes full EH info to be generated (not sure how to
split the metadata correctly).
MachineModuleInfo::needsFrameInfo is no longer used and
is removed.

llvm-svn: 49064

llvm-svn: 48805

llvm-svn: 48683

Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.

llvm-svn: 48380

Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. 

Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329

llvm-svn: 48257

llvm-svn: 47703

would have been a Godsend here!

llvm-svn: 47625

llvm-svn: 47300

llvm-svn: 46930

llvm-svn: 46667