- Mar 02, 2010
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Johnny Chen authored
Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing. Ref: A8.3 Conditional execution llvm-svn: 97571
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Johnny Chen authored
llvm-svn: 97567
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Xerxes Ranby authored
llvm-svn: 97565
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Xerxes Ranby authored
llvm-svn: 97564
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Chris Lattner authored
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader. Sink some other stuff out of DAGISelHeader into SDISel. Eliminate the various 'Indent' stuff from various targets, which dates to when isel was recursive. 17 files changed, 114 insertions(+), 430 deletions(-) llvm-svn: 97555
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Eric Christopher authored
Fixes PR5309. llvm-svn: 97554
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Bill Wendling authored
llvm-svn: 97536
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Dan Gohman authored
respectively. llvm-svn: 97531
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- Mar 01, 2010
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Chris Lattner authored
now that it is gone. llvm-svn: 97516
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Evan Cheng authored
Remove the optimize for code size limitation on r67917. Optimize 64-bit imul by constants into leas + shl regardless if optimizing for code size. The size saving from using imulq isn't worth it. Also, the lea and shl instructions may expose further optimization. llvm-svn: 97507
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Chris Lattner authored
problems. rdar://7697850. llvm-svn: 97500
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Chris Lattner authored
llvm-svn: 97485
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Johnny Chen authored
bit should be set to 0 instead of 1. llvm-svn: 97481
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Dan Gohman authored
llvm-svn: 97460
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Dan Gohman authored
llvm-svn: 97450
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Nathan Keynes authored
llvm-svn: 97443
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- Feb 28, 2010
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Mikhail Glushenkov authored
llvm-svn: 97427
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Chris Lattner authored
llvm-svn: 97374
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Dan Gohman authored
after LSR, so that clients can opt in. llvm-svn: 97357
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Dan Gohman authored
Extracting the low element of a vector is now done with EXTRACT_SUBREG, and the zero-extension performed by load movss is now modeled with SUBREG_TO_REG, and so on. Register-to-register movss and movsd are no longer considered copies; they are two-address instructions which insert a scalar into a vector. llvm-svn: 97354
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Dan Gohman authored
llvm-svn: 97348
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- Feb 27, 2010
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Chris Lattner authored
but codegen'd differently. This really wanted to use some sort of subreg to get the low 4 bytes of the G8RC register or something. However, it's invalid and nothing is testing it, so I'm just zapping the bogosity. llvm-svn: 97345
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Chris Lattner authored
llvm-svn: 97316
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Evan Cheng authored
llvm-svn: 97310
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- Feb 26, 2010
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Johnny Chen authored
o Parallel addition and subtraction, signed/unsigned o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8 o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16 o Signed multiply accumulate long (halfwords): SMLAL<x><y> o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X] o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X] llvm-svn: 97276
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Jakob Stoklund Olesen authored
This is possible because F8RC is a subclass of F4RC. We keep FMRSD around so fextend has a pattern. Also allow folding of memory operands on FMRSD. llvm-svn: 97275
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Jakob Stoklund Olesen authored
The PowerPC floating point registers can represent both f32 and f64 via the two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to allow cross-class coalescing. This coalescing only affects whether registers are spilled as f32 or f64. Spill slots must be accessed with load/store instructions corresponding to the class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking at the instruction opcode which is wrong. X86 has similar floating point register classes, but doesn't try to fold memory operands, so there is no problem there. llvm-svn: 97262
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Dale Johannesen authored
as X86 is currently the only FastISel target. Per review. llvm-svn: 97255
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Sanjiv Gupta authored
present in the module. llvm-svn: 97232
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Sanjiv Gupta authored
llvm-svn: 97228
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Dan Gohman authored
llvm-svn: 97227
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Richard Osborne authored
Previously LoopStrengthReduce would sometimes be unable to find a legal formula, causing an assertion failure. llvm-svn: 97226
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Chandler Carruth authored
llvm-svn: 97220
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Sanjiv Gupta authored
object construction. There is no provision to change them when the code for a function generated. So we have to change these names while printing assembly. llvm-svn: 97213
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Sanjiv Gupta authored
llvm-svn: 97211
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Dan Gohman authored
llvm-svn: 97201
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- Feb 25, 2010
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Johnny Chen authored
and SRS. llvm-svn: 97164
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Johnny Chen authored
llvm-svn: 97163
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Johnny Chen authored
llvm-svn: 97159
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Daniel Dunbar authored
llvm-svn: 97151
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