we need to generate a N64 compound relocation
R_MIPS_GPREL_32/R_MIPS_64/R_MIPS_NONE.

The bug was exposed by the SingleSourcetest case 
DuffsDevice.c.

Contributer: Jack Carter
llvm-svn: 172496

have an arbitrary ordering of the base register, index register and displacement.
rdar://12527141

llvm-svn: 172484

llvm-svn: 172483

llvm-svn: 172481

Refactor the big if/else sequence into one string switch for ARM subtype selection.

llvm-svn: 172475

Complete the existing support of ARM v6m, v7m, and v7em, i.e., respectively cortex-m0, cortex-m3, and cortex-m4 on the backend side.

Adds new subtype values for the MachO format and use them when the related triple are set.

llvm-svn: 172472

Fix a casting-away-const compiler warning.

llvm-svn: 172471

Properly cast code to eliminate cast-away-const errors.

llvm-svn: 172468

llvm-svn: 172379

Create a single multiclass for SSE and AVX version of MOVL/MOVH. Prevents needing to specify everything twice. No functional change intended

llvm-svn: 172378

llvm-svn: 172364

llvm-svn: 172358

Those can occur when something between the sextload and the store is on the same
chain and blocks isel. Fixes PR14887.

llvm-svn: 172353

MipsDisassembler.cpp: Prune DecodeHWRegs64RegisterClass() to suppress a warning. [-Wunused-function]

llvm-svn: 172319

llvm-svn: 172315

register names in the standalone assembler llvm-mc.

Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.


The problem is resolved by the Mips specific AsmParser 
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.


Contributer: Vladimir Medic
llvm-svn: 172284

Adds a check for -Oz, changes the code to not re-visit BBs,
and skips over DBG_VALUE instrs.

Patch by Andy Zhang.

llvm-svn: 172258

llvm-svn: 172157

llvm-svn: 172151

r172121.

llvm-svn: 172148

Part of rdar://12991541

llvm-svn: 172121

llvm-svn: 172011

ARM Cost model: Use the size of vector registers and widest vectorizable instruction to determine the max vectorization factor.

llvm-svn: 172010

 
This patch adjust the r171506 to make all DWARF enconding pc-relative
for PPC64. It also adds the R_PPC64_REL32 relocation handling in MCJIT
(since the eh_frame will not generate PIC-relative relocation) and also
adds the emission of stubs created by the TTypeEncoding.

llvm-svn: 171979

PR 14848. The lowered sequence is based on the existing sequence the target-independent
DAG Combiner creates for the scalar case.

Patch by Zvi Rackover.

llvm-svn: 171953

address space. Reordered the EmitULEB128IntValue arguments to
make this easier.

llvm-svn: 171949

This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.

I converted some in-order scheduling tests to A2. Hal is working on
more test cases.

llvm-svn: 171946

them.

llvm-svn: 171933

Cost Model: Move the 'max unroll factor' variable to the TTI and add initial Cost Model support on ARM.

llvm-svn: 171928

an R_MIPS_GPREL16 relocation.


Contributer: Jack Carter
llvm-svn: 171882

value in the 64 bit .eh_frame section.

It doesn't however allow exception handling to work
yet since it depends on the correct relocation model
being set in the ELF header flags.


Contributer: Jack Carter
llvm-svn: 171881

The current Intel Atom microarchitecture has a feature whereby
when a function returns early then it is slightly faster to execute
a sequence of NOP instructions to wait until the return address is ready,
as opposed to simply stalling on the ret instruction until
the return address is ready.

When compiling for X86 Atom only, this patch will run a pass,
called "X86PadShortFunction" which will add NOP instructions where less
than four cycles elapse between function entry and return.

It includes tests.

This patch has been updated to address Nadav's review comments
- Optimize only at >= O1 and don't do optimization if -Os is set
- Stores MachineBasicBlock* instead of BBNum
- Uses DenseMap instead of std::map
- Fixes placement of braces

Patch by Andy Zhang.

llvm-svn: 171879

No change in functionality.

llvm-svn: 171822

llvm-svn: 171790

s/X86/ARM/

llvm-svn: 171789

code generation.  Variables addressed through a GlobalAlias were not being
handled, and variables with available_externally linkage were treated
incorrectly.  The patch contains two new tests to verify the correct code
generation for these cases.

llvm-svn: 171778

This is necessary not only for representing empty ranges, but for handling
multibyte characters in the input. (If the end pointer in a range refers to
a multibyte character, should it point to the beginning or the end of the
character in a char array?) Some of the code in the asm parsers was already
assuming this anyway.

llvm-svn: 171765

llvm-svn: 171728

Absent a Contributor's License Agreement (CLA) with an LLVM legal entity and as
reviewed and agreed with Chris Lattner, add a patent license covering future
contributions from ARM until there is a CLA. This is to make explicit ARM's
grant of patent rights to recipients of LLVM containing ARM-contributed
material.

llvm-svn: 171721

llvm-svn: 171702