with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.

llvm-svn: 139159

Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745

llvm-svn: 139157

Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).

llvm-svn: 139155

llvm-svn: 139154

llvm-svn: 139148

init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC.  While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function.  To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function.  Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!).  Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC.  Patch mostly by Sanjoy Das.

llvm-svn: 139140

instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!

llvm-svn: 139125

llvm-svn: 139124

llvm-svn: 139122

llvm-svn: 139079

the cycle of missing AVX counterparts of already present SSE* patterns

llvm-svn: 139073

llvm-svn: 139072

llvm-svn: 139071

llvm-svn: 139070

llvm-svn: 139069

duplicate it for AVX mode.

llvm-svn: 139068

llvm-svn: 139067

that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.

llvm-svn: 139066

pattern should be matched

llvm-svn: 139065

llvm-svn: 139064

it!

llvm-svn: 139063

llvm-svn: 139062

llvm-svn: 139061

OptForSize pattern

llvm-svn: 139060

The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

llvm-svn: 139057

It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.

llvm-svn: 139056

llvm-svn: 139055

llvm-svn: 139053

Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.

llvm-svn: 139049

llvm-svn: 139047

llvm-svn: 139044

For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.

llvm-svn: 139040

case those instructions that the immediate is not sign-extend.  radr://8795217

llvm-svn: 139028

llvm-svn: 139024

llvm-svn: 139022

llvm-svn: 139021

llvm-svn: 139018

llvm-svn: 139017

llvm-svn: 139004

llvm-svn: 138982