commit a LOT of files.

llvm-svn: 35858

llvm-svn: 35850

llvm-svn: 35847

llvm-svn: 35840

llvm-svn: 35834

llvm-svn: 35817

1. Fix some bugs in the jump table lowering threshold
2. Implement much better metric for optimal pivot selection
3. Tune thresholds for different lowering methods
4. Implement shift-and trick for lowering small (<machine word
length) cases with few destinations. Good testcase will follow.

llvm-svn: 35816

Adapt handling of parameter attributes to use the new ParamAttrsList class.

llvm-svn: 35814

llvm-svn: 35802

llvm-svn: 35800

instructions which replace themselves when FI's are rewritten (common on ppc).
This fixes CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll

llvm-svn: 35789

some instructions can have multiple frame indices in them.  If this happens,
rewrite all of them.

llvm-svn: 35785

llvm-svn: 35783

llvm-svn: 35779

llvm-svn: 35696

llvm-svn: 35679

llvm-svn: 35678

go to the same destination. Now we're producing really good code for
switch-lower-feature.ll testcase

llvm-svn: 35672

llvm-svn: 35660

Trivially re-materializable instructions have spill weights that are half of what it would be otherwise.

llvm-svn: 35658

llvm-svn: 35618

2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.

llvm-svn: 35605

llvm-svn: 35600

Make sure that the CTPOP result is casted to i32 as the bit counting
intrinsics all return i32 now (this affects CTLZ and CTTZ as well).

llvm-svn: 35567

Support overloaded intrinsics bswap, ctpop, cttz, ctlz.

llvm-svn: 35547

Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.

llvm-svn: 35546

Change getOperationName to return std::string instead of const char*

llvm-svn: 35545

llvm-svn: 35529

llvm-svn: 35527

llvm-svn: 35522

llvm-svn: 35520

combination.

llvm-svn: 35517

register more than once.

llvm-svn: 35513

of dead def live interval at 1 to avoid multiple def's targeting the same
register. The previous patch missed a case where the source operand is live-in.
In that case, remove the whole interval.

llvm-svn: 35512

big endian targets until llvm-gcc build issue has been resolved.

llvm-svn: 35449

llvm-svn: 35445

llvm-svn: 35420

llvm-svn: 35419

llvm-svn: 35407

llvm-svn: 35406