llvm-svn: 134224

llvm-svn: 134223

supporting the instruction that the constraint is for 'movw'.

Part of rdar://9119939

llvm-svn: 134222

llvm-svn: 134221

for the 'x' register constraint.

Part of rdar://9119939

llvm-svn: 134220

llvm-svn: 134219

Part of rdar://9119939

llvm-svn: 134217

llvm-svn: 134216

Part of rdar://9307836 and rdar://9119939

llvm-svn: 134215

llvm-svn: 134212

llvm-svn: 134211

llvm-svn: 134210

llvm-svn: 134209

llvm-svn: 134208

We would put the return value from long double functions in the wrong
register.

This fixes gcc.c-torture/execute/conversion.c

llvm-svn: 134205

Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.

llvm-svn: 134204

Part of rdar://9119939

llvm-svn: 134203

encoding for the registers it knows about. Return -1 if it can't handle that
register.

llvm-svn: 134202

llvm-svn: 134201

llvm-svn: 134200

A = X
B = X

Instead, proceed as if we had found

A = X
B = A

llvm-svn: 134199

No functional change.

Part of rdar://9119939

llvm-svn: 134198

Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.

llvm-svn: 134197

llvm-svn: 134196

llvm-svn: 134194

llvm-svn: 134193

llvm-svn: 134191

llvm-svn: 134189

nodes.

Original message:
Let simplify cfg simplify bb with only debug and lifetime intrinsics.

llvm-svn: 134182

It's just a call to a special helper function. Get rid of the T2 variant
entirely, as it's identical to the Thumb1 version.

llvm-svn: 134178

llvm-svn: 134177

It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.

llvm-svn: 134173

It's just a tPOP instruction with additional code-gen properties, so it
doesn't need encoding information.

llvm-svn: 134172

llvm-svn: 134148

llvm-svn: 134134

llvm-svn: 134131

tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the
predicate is anything other than "always."

llvm-svn: 134130

llvm-svn: 134129

be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!

llvm-svn: 134127

llvm-svn: 134126