- Oct 13, 2009
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Ted Kremenek authored
llvm-svn: 84008
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Bob Wilson authored
Patch by Johnny Chen. llvm-svn: 83983
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Bob Wilson authored
llvm-svn: 83982
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Bob Wilson authored
llvm-svn: 83973
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Kevin Enderby authored
llvm-svn: 83917
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Bob Wilson authored
before its reference is only supported on ARM has not been true for a while. In fact, until recently, that was only supported for Thumb. Besides that, CPEs are always a multiple of 4 bytes in size, so inserting a CPE should have no effect on Thumb alignment. llvm-svn: 83916
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Kevin Enderby authored
should have been a pointer to a reference. llvm-svn: 83915
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- Oct 12, 2009
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Bob Wilson authored
llvm-svn: 83905
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Bob Wilson authored
MultiSource/Benchmarks/MiBench/automotive-susan test. The failure has since been masked by an unrelated change (just randomly), so I don't have a testcase for this now. Radar 7291928. The situation where this happened is that a constant pool entry (CPE) was placed at a lower address than the load that referenced it. There were in fact 2 CPEs placed at adjacent addresses and referenced by 2 loads that were close together in the code. The distance from the loads to the CPEs was right at the limit of what they could handle, so that only one of the CPEs could be placed within range. On every iteration, the first CPE was found to be out of range, causing a new CPE to be inserted. The second CPE had been in range but the newly inserted entry pushed it too far away. Thus the second CPE was also replaced by a new entry, which in turn pushed the first CPE out of range. Etc. Judging from some comments in the code, the initial implementation of this pass did not support CPEs placed _before_ their references. In the case where the CPE is placed at a higher address, the key to making the algorithm terminate is that new CPEs are only inserted at the end of a group of adjacent CPEs. This is implemented by removing a basic block from the "WaterList" once it has been used, and then adding the newly inserted CPE block to the list so that the next insertion will come after it. This avoids the ping-pong effect where CPEs are repeatedly moved to the beginning of a group of adjacent CPEs. This does not work when going backwards, however, because the entries at the end of an adjacent group of CPEs are closer than the CPEs earlier in the group. To make this pass terminate, we need to maintain a property that changes can only happen in some sort of monotonic fashion. The fix used here is to require that the CPE for a particular constant pool load can only move to lower addresses. This is a very simple change to the code and should not cause any significant degradation in the results. llvm-svn: 83902
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Bob Wilson authored
llvm-svn: 83897
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Bob Wilson authored
llvm-svn: 83894
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Bob Wilson authored
llvm-svn: 83874
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Bob Wilson authored
llvm-svn: 83873
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Bob Wilson authored
llvm-svn: 83872
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Dale Johannesen authored
bootstrap of FSF-style PPC, so there is some reason to believe the original bug (which was never analyzed) has been fixed, probably by 82266. llvm-svn: 83871
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Dan Gohman authored
it to hold the address of an sret return value, for x86-64 ABI purposes. Also, fix the test that was originally intended to test this to actually test it, using FileCheck. llvm-svn: 83853
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Chris Lattner authored
llvm-svn: 83822
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Anton Korobeynikov authored
llvm-svn: 83812
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Anton Korobeynikov authored
llvm-svn: 83811
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- Oct 11, 2009
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Anton Korobeynikov authored
llvm-svn: 83785
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Anton Korobeynikov authored
Implement proper asmprinting for the globals. This eliminates bogus "call" modifier and also adds support for offsets wrt globals. llvm-svn: 83784
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Anton Korobeynikov authored
llvm-svn: 83783
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Anton Korobeynikov authored
Remove impdef of SRW. This fixes PR4779 llvm-svn: 83739
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- Oct 10, 2009
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Dan Gohman authored
llvm-svn: 83697
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Dan Gohman authored
MachineInstr::isInvariantLoad instead, which has the benefit of being more complete. llvm-svn: 83696
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Dan Gohman authored
when loading from an invariant memory location. llvm-svn: 83688
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Dan Gohman authored
llvm-svn: 83677
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- Oct 09, 2009
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Kevin Enderby authored
lists. Changed ARMAsmParser::MatchRegisterName to return -1 instead of 0 on errors so 0-15 values could be returned as register numbers. Also added the rest of the arm register names to the currently hacked up version to allow more testing. Some changes to ARMAsmParser::ParseOperand to give different errors for things not yet supported and some additions to the hacked ARMAsmParser::MatchInstruction to allow more testing for now. llvm-svn: 83673
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Dan Gohman authored
when one of the bits being tested would end up being the sign bit in the narrower type, and a signed comparison is being performed, since this would change the result of the signed comparison. This fixes PR5132. llvm-svn: 83670
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Dan Gohman authored
information when unfolding memory references. llvm-svn: 83656
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Bob Wilson authored
llvm-svn: 83600
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Bob Wilson authored
llvm-svn: 83598
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Bob Wilson authored
llvm-svn: 83596
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Bob Wilson authored
Also fix some copy-and-paste errors in previous changes. llvm-svn: 83590
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Bob Wilson authored
llvm-svn: 83585
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- Oct 08, 2009
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Anton Korobeynikov authored
llvm-svn: 83572
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Bob Wilson authored
llvm-svn: 83568
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Bob Wilson authored
llvm-svn: 83566
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Bob Wilson authored
llvm-svn: 83565
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Richard Osborne authored
llvm-svn: 83556
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