CoalescerPair can determine if a copy can be coalesced, and which register gets
merged away. The old logic in SimpleRegisterCoalescing had evolved into
something a bit too convoluted.

llvm-svn: 106701

llvm-svn: 106699

Do not use "ValueMap" as a name for a local variable or an argument.

llvm-svn: 106698

llvm-svn: 106697

void t(int *cp0, int *cp1, int *dp, int fmd) {
  int c0, c1, d0, d1, d2, d3;
  c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000);
  /* ... */
}

It code gens into something pretty bad. But with this change (analogous to the
X86 back-end), it will use ldm and generate few instructions.

llvm-svn: 106693

llvm-svn: 106692

llvm-svn: 106686

llvm-svn: 106685

llvm-svn: 106683

Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction

llvm-svn: 106678

llvm-svn: 106677

having a library both as bitcode and native code. We want to use the
bitcode first, but if codegen produces new undefined references we have to use
the native code to satisfy those references.

Gold has no notion of bitcode and native search directories, so instead it has
an API where the plugin can instruct it to look for the libraries it is passing
to it. This patch uses that API.

llvm-svn: 106674

llvm-svn: 106672

llvm-svn: 106671

Given the pattern below as an example:
list<dag> Pattern = [(set RC:$dst, (v4f32 (shufp:src3 RC:$src1,
                            (mem_frag addr:$src2))))];

The right reference resolving should lead to:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp:src3 VR128:$src1,
                            (mem_frag addr:$src2))))];
But was yielding:
list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp VR128:$src1,
                            (mem_frag addr:$src2))))];

Fix this by passing the right name when creating a new DagInit node.

llvm-svn: 106670

llvm-svn: 106664

llvm-svn: 106663

branch turns out to be ARM-to-Thumb or vice versa
the linker cannot resolve this.  8120438.

If this optimization is going to be useful we probably
need a compiler flag "assume callees are same architecture"
or something like that.

llvm-svn: 106662

into the same node, but with different non-memory operands, we need to replace
the memory operands after it's finished morphing.

llvm-svn: 106643

llvm-svn: 106638

Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.

llvm-svn: 106634

to using that.

llvm-svn: 106633

MEMBARRIER fences aren't necessary for ARM. Tell the combiner to fold them
away.

llvm-svn: 106631

atomic intrinsics, either because the use locking instructions for the
atomics, or because they perform the locking directly. Add support in the
DAG combiner to fold away the fences.

llvm-svn: 106630

llvm-svn: 106628

llvm-svn: 106627

llvm-svn: 106626

llvm-svn: 106623

llvm-svn: 106622

llvm-svn: 106621

Haiku like Linux provides <regex.h>, so use it. Patch by Paul Davey!

llvm-svn: 106620

Revert r106066, "Create a more targeted fix for not sinking instructions into a range where it"... it causes bzip2 to be miscompiled by Clang.

Conflicts:

	lib/CodeGen/MachineSink.cpp

llvm-svn: 106614

llvm-svn: 106611

Thanks Daniel!

llvm-svn: 106608

later on. But we need them saved in the symbols directory.

llvm-svn: 106604

Replace ScalarEvolution's private copy of getLoopPredecessor
with LoopInfo's public copy.

llvm-svn: 106603

llvm-svn: 106600

allocation details.

llvm-svn: 106599

llvm-svn: 106598

is another max which folds. This fixes PR7454.

llvm-svn: 106594