Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024

 - Some clients which used DOUT have moved to DEBUG. We are deprecating the
   "magic" DOUT behavior which avoided calling printing functions when the
   statement was disabled. In addition to being unnecessary magic, it had the
   downside of leaving code in -Asserts builds, and of hiding potentially
   unnecessary computations.

llvm-svn: 77019

llvm-svn: 77018

Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types.  More to come.

llvm-svn: 77011

llvm-svn: 77004

Disable my constant island pass optimization (to make use soimm more effectively). It caused infinite looping on lencod.

llvm-svn: 76995

Add a workaround for Darwin assembler bug where it's not setting the thumb bit in Thumb2 jumptable entries. We now pass Olden.

llvm-svn: 76991

llvm-svn: 76986

llvm-svn: 76984

llvm-svn: 76983

llvm-svn: 76960

llvm-svn: 76944

llvm-svn: 76941

llvm-svn: 76930

FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets.

llvm-svn: 76925

Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.

llvm-svn: 76919

llvm-svn: 76909

Also fixed up code to fully use the SoImm field for ADR on ARM mode.

llvm-svn: 76890

Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address.

Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.

llvm-svn: 76889

Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.

llvm-svn: 76883

llvm-svn: 76872

llvm-svn: 76806

llvm-svn: 76803

llvm-svn: 76762

llvm-svn: 76729

Add R12 to the list of registers clobbered by 16-bit Thumb calls as a pre-caution. r12 could be live once we have mixed 32-bit and 16-bit instructions.

llvm-svn: 76728

llvm-svn: 76727

llvm-svn: 76725

llvm-svn: 76711

llvm-svn: 76702

negative on an individual bases rather than basing on whether it's in thumb
mode.

llvm-svn: 76698

llvm-svn: 76693

llvm-svn: 76679

pool entry will require relocations against it.  I implemented this
conservatively for ARM, someone who is knowledgable about it should
see if this can be improved.

llvm-svn: 76678

llvm-svn: 76612

and call PrintGlobalVariable, allowing elimination and simplification
of various targets.

llvm-svn: 76604

llvm-svn: 76600

llvm-svn: 76520

llvm-svn: 76489

llvm-svn: 76456