llvm-svn: 133390

llvm-svn: 133389

llvm-svn: 133388

instead of scalarizing, and doing an element-by-element truncat.

llvm-svn: 133382

llvm-svn: 133381

expressions, but Chris wants to instead reduce the set of possible constant
expression types.

llvm-svn: 133374

can manipulate instructions and constantexpr's uniformly. No users yet though.

llvm-svn: 133373

top level type without a specified number.  This syntax isn't documented
and blocks forward progress.

llvm-svn: 133371

llvm-svn: 133369

top level type without a specified number.  This asmprinter has never
generated this, as you can tell by no tests being updated.  It also isn't
documented.

llvm-svn: 133368

much cleaner.

llvm-svn: 133364

llvm-svn: 133363

llvm-svn: 133362

now that Type::getDescription() is dead, the TypePrinting class can move from Assembly/Writer.h to being 
a private class in AsmWriter.cpp.

llvm-svn: 133361

removes some gunk from LLVMContext.

llvm-svn: 133360

llvm-svn: 133359

llvm-svn: 133356

temporary std::string for every function being checked.

llvm-svn: 133355

llvm-svn: 133352

llvm-svn: 133351

llvm-svn: 133350

llvm-svn: 133349

llvm-svn: 133348

llvm-svn: 133347

In cases such as the attached test, where the case value for a switch
destination is used in a phi node that follows the destination, it
might be better to replace that value with the condition value of the
switch, so that more blocks can be folded away with
TryToSimplifyUncondBranchFromEmptyBlock because there are less
conflicts in the phi node.

llvm-svn: 133344

llvm-svn: 133339

type's bitwidth matches the (allocated) size of the alloca. This severely
pessimizes vector scalar replacement when the only vector type being used is
something like <3 x float> on x86 or ARM whose allocated size matches a
<4 x float>.

I hope to fix some of the flawed assumptions about allocated size throughout
scalar replacement and reenable this in most cases.

llvm-svn: 133338

for pre-2.9 bitcode files.  We keep x86 unaligned loads, movnt, crc32, and the
target indep prefetch change.

As usual, updating the testsuite is a PITA.

llvm-svn: 133337

alloca. Fixes part of <rdar://problem/9580800>.

llvm-svn: 133336

unless ScalarKind is Vector.

llvm-svn: 133335

This should fix the Linux buildbots.

llvm-svn: 133334

Reuse the CodeGenRegBank DenseMap in a few places that would build their
own or use linear search.

llvm-svn: 133333

Targets that need to change the default allocation order should use the
AltOrders mechanism instead. See the X86 and ARM targets for examples.

The allocation_order_begin() and allocation_order_end() methods have been
replaced with getRawAllocationOrder(), and there is further support
functions in RegisterClassInfo.

It is no longer possible to insert arbitrary code into generated
register classes. This is a feature.

llvm-svn: 133332

llvm-svn: 133331

This slightly changes the GPR allocation order on Darwin where R9 is not
a callee-saved register:

Before: %R0 %R1 %R2 %R3 %R12 %R9 %LR %R4 %R5 %R6 %R8 %R10 %R11
After:  %R0 %R1 %R2 %R3 %R9 %R12 %LR %R4 %R5 %R6 %R8 %R10 %R11
llvm-svn: 133326

llvm-svn: 133325

llvm-svn: 133324

llvm-svn: 133321

A register class can define AltOrders and AltOrderSelect instead of
defining method protos and bodies. The AltOrders lists can be defined
with set operations, and TableGen can verify that the alternative
allocation orders only contain valid registers.

This is currently an opt-in feature, and it is still possible to
override allocation_order_begin/end. That will not be true for long.

llvm-svn: 133320

* Make this used only if CFI is used.

llvm-svn: 133319