Use iPTR instead of i32 for extract_subvector/insert_subvector index in lowering and patterns. This makes it consistent with the incoming DAG nodes from the DAG builder.

llvm-svn: 163293

Add patterns for converting stores of subvector_extracts of lower 128-bits of a 256-bit vector to VMOVAPSmr/VMOVUPSmr.

llvm-svn: 163292

This reverts commit 163278.

Works OK on x86_64, but not i386. Will re-enable when that's cleared up.

llvm-svn: 163290

llvm-svn: 163289

llvm-svn: 163288

assembler such as shifts greater than 32. In the case 
of direct object, the code gen needs to do this lowering 
since the assembler is not involved.

With the advent of the llvm-mc assembler, it also needs 
to do the same lowering.

This patch makes that specific lowering code accessible 
to both the direct object output and the assembler.

This patch does not affect generated output.

llvm-svn: 163287

No functional change.

llvm-svn: 163279

llvm-svn: 163278

Test case included.

Contributer: Vladimir Medic
llvm-svn: 163277

llvm-svn: 163276

These pseudos are no longer needed now that it is possible to represent
predicated instructions in SSA form.

llvm-svn: 163275

Now that it is possible to dynamically tie MachineInstr operands,
predicated instructions are possible in SSA form:

  %vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg
  %vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR

Becomes a predicated SUBri with a tied imp-use:

  SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0>

This means that any instruction that is safe to move can be folded into
a MOVCC, and the *CC pseudo-instructions are no longer needed.

The test case changes reflect that Thumb2SizeReduce recognizes the
predicated instructions. It didn't understand the pseudos.

llvm-svn: 163274

llvm-svn: 163273

llvm-svn: 163272

every relocation in C++ hello world built with debug info.

llvm-svn: 163271

switch, make sure we include the value for the cases when calculating edge
value from switch to the default destination.

rdar://12241132

llvm-svn: 163270

register support. Test case included.

Contributer: Vladimir Medic
llvm-svn: 163268

llvm-svn: 163263

llvm-svn: 163258

MachineInstr.

llvm-svn: 163257

llvm-svn: 163256

ArchiveMemberHeader. Found by gcc48 -Wcast-qual.

llvm-svn: 163255

of its constness. Found by gcc48 -Wcast-qual.

llvm-svn: 163254

the SubtargetInfoKV tables. Found by gcc48 -Wcast-qual.

llvm-svn: 163251

by casting. Found with gcc48.

llvm-svn: 163247

llvm-svn: 163243

llvm-svn: 163242

llvm-svn: 163241

Avoid interleaving fprintf(stderr,...) and outs() << ...;

Also add a column to show "bytes-per" for each record.

llvm-svn: 163240

llvm-svn: 163235

Since TOC is just defined for PPC64, move its definition to PPC64 td file.

Patch by Adhemerval Zanella.

llvm-svn: 163234

llvm-svn: 163233

inteldialect.

llvm-svn: 163231

Previous patch accidentally decided it couldn't convert a VFP to a
NEON instruction after it had already destroyed the old one. Not a
good move.

llvm-svn: 163230

llvm-svn: 163229

llvm-svn: 163228

llvm-svn: 163225

Make sure to return a pointer into the target memory, not the local memory.
Often they are the same, but we can't assume that.

llvm-svn: 163217

Simulate a remote target address space by allocating a seperate chunk of
memory for the target and re-mapping section addresses to that prior to
execution. Later we'll want to have a truly remote process, but for now
this gets us closer to being able to test the remote target
functionality outside LLDB.

rdar://12157052

llvm-svn: 163216

It relies on clear() being fast and the cache rarely has more than 1 or 2
elements, so give it an inline capacity and always shrink it back down in case
it grows. DenseMap will grow to 64 buckets which makes clear() a lot slower.

llvm-svn: 163215