Fix a leak that this turned up in LowerSubregs.cpp.
And, comment a leak in LiveIntervalAnalysis.cpp.

llvm-svn: 53746

PseudoSourceValue values, which never have names. Use getName()
for all other values, because we want to print just a short summary
of the value, not the entire instruction.

llvm-svn: 53738

llvm-svn: 53734

mask.  These are just indices into the shuffled vector
so their type is unrelated to the type of the
shuffled elements (which is what was being used before).
This fixes vec_shuffle-11.ll when using LegalizeTypes.
What seems to have happened is that Dan's recent change
r53687, which corrected the result type of the shuffle,
somehow caused LegalizeTypes to notice that the mask
operand was a BUILD_VECTOR with a legal type but elements
of an illegal type (i64).  LegalizeTypes legalized this
by introducing a new BUILD_VECTOR of i32 and bitcasting
it to the old type.  But the mask operand is not supposed
to be a bitcast but a straight BUILD_VECTOR of constants,
causing a crash.

llvm-svn: 53729

replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.

Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.

This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.

These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.

llvm-svn: 53728

only missing ppc long double operations: FNEG
and FP_EXTEND.

llvm-svn: 53723

it is breaking Darwin bootstrap due to missing
functionality.

llvm-svn: 53721

llvm-svn: 53713

was turned up by some new SelectionDAG assertion checks that I'm
working on.

llvm-svn: 53687

and AssertSext.  Needed when passing huge integer
parameters with the zeroext or signext attributes.

llvm-svn: 53684

llvm-svn: 53681

llvm-svn: 53680

While this is not a wonderful organizing principle, it
does make it easy to find routines, and clear where to
insert new ones.

llvm-svn: 53672

llvm-svn: 53671

llvm-svn: 53636

just use the AllNodes order, which is at least relatively stable
across runs.

llvm-svn: 53632

llvm-svn: 53613

In LegalizeDAG the value is zero-extended to
the new type before byte swapping.  It doesn't
matter how the extension is done since the new
bits are shifted off anyway after the swap, so
extend by any old rubbish bits.  This results
in the final assembler for the testcase being
one line shorter.

llvm-svn: 53604

llvm-svn: 53603

No change in functionality.

llvm-svn: 53602

llvm-svn: 53590

the BB member to the current basic block after emitting
instructions.

llvm-svn: 53567

don't have value names, so use print instead of getName() to get a
useful string.

llvm-svn: 53563

llvm-svn: 53562

Remove support for this.

llvm-svn: 53559

non-power-of-two vectors.

llvm-svn: 53558

than the vector element type.  Don't forget to
handle this when the insertion index is not a
constant.

llvm-svn: 53556

extending load of a vector.  Handle this case when
splitting vector loads.  I'm not completely sure
what is supposed to happen, but I think it means
hi should be set to undef.  LegalizeDAG does not
consider this case.

llvm-svn: 53555

stores of one-element vectors.  Also, neaten the
handling of INSERT_VECTOR_ELT when the inserted
type is larger than the vector element type.

llvm-svn: 53554

are used for passing huge immediates in inline ASM
from the front-end straight down to the ASM writer.
Of course this is a hack, but it is simple, limited
in scope, works in practice, and is what LegalizeDAG
does.

llvm-svn: 53553

llvm-svn: 53504

Fix PR2536: a nasty spiller bug. If a two-address instruction uses a register but the use portion of its live range is not part of its liveinterval, it must be defined by an implicit_def. In that case, do not spill the use. e.g.
8   %reg1024<def> = IMPLICIT_DEF
12  %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2

The live range [12, 14) are not part of the r1024 live interval since it's defined by an implicit def. It will not conflicts with live interval of r1025. Now suppose both registers are spilled, you can easily see a situation where both registers are reloaded before the INSERT_SUBREG and both target registers that would overlap.

llvm-svn: 53503

llvm-svn: 53502

instead of using the frame index for the SVOffset, which was
inconsistent.

llvm-svn: 53486

llvm-svn: 53481

llvm-svn: 53480

use a timer group for the timers in SelectionDAGISel. Also,
Split scheduling out from emitting, to give each their own
timer.

llvm-svn: 53476

llvm-svn: 53471

be no need to split the result of a vector RET node,
since they are always already legal.

llvm-svn: 53462

SINT_TO_FP libcall plus additional operations:
it might as well be a direct UINT_TO_FP libcall.
So only turn it into an SINT_TO_FP if the target
has special handling for SINT_TO_FP.

llvm-svn: 53461