a while ago.  We now produce:

_foo:
	mflr r0
	std r0, 16(r1)
	ld r2, 16(r1)
	std r2, 0(r3)
	ld r0, 16(r1)
	mtlr r0
	blr 

instead of:

_foo:
	mflr r0
	std r0, 16(r1)
	lis r0, 0
	ori r0, r0, 16
	ldx r2, r1, r0
	std r2, 0(r3)
	ld r0, 16(r1)
	mtlr r0
	blr 

for:

void foo(void **X) {
  *X = __builtin_return_address(0);
}

on ppc64.

llvm-svn: 44701

llvm-svn: 44700

different places to mean different things.  Document what the
one in PPCFunctionInfo means and when it is valid.

llvm-svn: 44699

llvm-svn: 44697

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20071203/056043.html
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20071203/056048.html

llvm-svn: 44696

Fix several cache coherence bugs in MemDep/GVN that were found.  Also add some (disabled) debugging code
to make such problems easier to diagnose in the future, written by Duncan Sands.

llvm-svn: 44695

llvm-svn: 44694

llvm-svn: 44692

llvm-svn: 44691

llvm-svn: 44690

_foo:
        li r2, 0
LBB1_1: ; bb
        li r5, 0
        stw r5, 0(r3)
        addi r2, r2, 1
        addi r3, r3, 4
        cmplw cr0, r2, r4
        bne cr0, LBB1_1 ; bb
LBB1_2: ; return
        blr 

to:

_foo:
        li r2, 0
        li r5, 0
LBB1_1: ; bb
        stw r5, 0(r3)
        addi r2, r2, 1
        addi r3, r3, 4
        cmplw cr0, r2, r4
        bne cr0, LBB1_1 ; bb
LBB1_2: ; return
        blr

ZOMG!! :-)

Moar to come...

llvm-svn: 44687

llvm-svn: 44686

llvm-svn: 44676

llvm-svn: 44674

llvm-svn: 44672

llvm-svn: 44671

Remove a bogus optimization. It's not possible to do a move to low element to a <8 x i16> or <16 x i8> vector.

llvm-svn: 44669

llvm-svn: 44668

Simpler and safer.

llvm-svn: 44663

llvm-svn: 44660

only disable it if we don't know it will be obviously profitable.
Still fixme, but less so. :)

llvm-svn: 44658

the X86 backend are needed before this should be enabled by default.

llvm-svn: 44657

_foo:
	movl	$12, %eax
	andl	4(%esp), %eax
	movl	_array(%eax), %eax
	ret

instead of:

_foo:
	movl	4(%esp), %eax
	shrl	$2, %eax
	andl	$3, %eax
	movl	_array(,%eax,4), %eax
	ret

As it turns out, this triggers all the time, in a wide variety of
situations, for example, I see diffs like this in various programs:

-       movl    8(%eax), %eax
-       shll    $2, %eax
-       andl    $1020, %eax
-       movl    (%esi,%eax), %eax
+       movzbl  8(%eax), %eax
+       movl    (%esi,%eax,4), %eax


-       shll    $2, %edx
-       andl    $1020, %edx
-       movl    (%edi,%edx), %edx
+       andl    $255, %edx
+       movl    (%edi,%edx,4), %edx

Unfortunately, I also see stuff like this, which can be fixed in the
X86 backend:

-       andl    $85, %ebx
-       addl    _bit_count(,%ebx,4), %ebp
+       shll    $2, %ebx
+       andl    $340, %ebx
+       addl    _bit_count(%ebx), %ebp

llvm-svn: 44656

llvm-svn: 44655

llvm-svn: 44654

llvm-svn: 44651

llvm-svn: 44650

llvm-svn: 44649

to create a JIT.  This lets you specify JIT-specific configuration items
like the JITMemoryManager to use.

llvm-svn: 44647

delete one ExecutionEngine ctor, minor cleanup.

llvm-svn: 44646

llvm-svn: 44645

Fix for PR1831: if all defs of an interval are re-materializable, then it's a preferred spill candiate.

llvm-svn: 44644

If both result of the {s|z}xt and its source are live out, rewrite all uses of the source with result of extension.

llvm-svn: 44643

llvm-svn: 44641

own JITMemoryManager interface.  There is no functionality change with 
this patch.

llvm-svn: 44640

llvm-svn: 44638

llvm-svn: 44637

llvm-svn: 44629

llvm-svn: 44628

- Fix typo in SPUCallingConv.td
- Credit myself for CellSPU work
- Add CellSPU to 'all' host target list

llvm-svn: 44627