llvm-svn: 105303

in X86FastISel. Patch by Jan Sjodin.

llvm-svn: 105290

llvm-svn: 105276

llvm-svn: 105269

llvm-svn: 105109

llvm-svn: 105108

llvm-svn: 105107

llvm-svn: 105106

Fix PR7193: if sibling call address can take a register, make sure there are enough registers available by counting inreg arguments.

llvm-svn: 105092

were overspecified when inheriting sub-subregisters, for instance:

R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit.

This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous.

llvm-svn: 105063

Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.

llvm-svn: 105060

llvm-svn: 105059

llvm-svn: 105014

llvm-svn: 105005

llvm-svn: 105001

getX86RegNum() does not happen.  Patch by Shantonu Sen!

llvm-svn: 104994

llvm-svn: 104980

llvm-svn: 104974

make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.

llvm-svn: 104967

the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.

llvm-svn: 104907

an alloca() or an llvm.stackrestore(). rdar://8031573

llvm-svn: 104900

llvm-svn: 104899

llvm-svn: 104897

llvm-svn: 104891

llvm-svn: 104890

should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.

llvm-svn: 104883

No functional effect as these nodes are not generated yet.

llvm-svn: 104879

To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.

llvm-svn: 104866

to update the jmpbuf in the presence of VLAs.

llvm-svn: 104862

common code between SSE versions.

llvm-svn: 104860

to be matched.

llvm-svn: 104757

TableGen shortly.

llvm-svn: 104754

-filetype=obj.

llvm-svn: 104747

This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...

llvm-svn: 104745

ISD::. No functional change.

llvm-svn: 104734

llvm-svn: 104731

llvm-svn: 104713

llvm-svn: 104711

before encoding.

llvm-svn: 104707

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704