appropriate for targets without detailed instruction iterineries.
The scheduler schedules for increased instruction level parallelism in
low register pressure situation; it schedules to reduce register pressure
when the register pressure becomes high.

On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2
by 16%.

llvm-svn: 109300

to be of a different register class. For example, in Thumb1 if the live-in is
a high register, we want the vreg to be a low register. rdar://8224931

llvm-svn: 109291

llvm-svn: 109285

  it's too late to start backing off aggressive latency scheduling when most
  of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
  For ARM, this is almost always a win on # of instructions. It's runtime
  neutral for most of the tests. But for some kernels with high register
  pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
  54 and sped up by 20%.

llvm-svn: 109279

llvm-svn: 109265

llvm-svn: 109262

are not demanded. This often allows the anyext to be folded away.

llvm-svn: 109242

llvm-svn: 109234

llvm-svn: 109205

llvm-svn: 109167

llvm-svn: 109122

llvm-svn: 109103

llvm-svn: 109092

llvm-svn: 109083

llvm-svn: 109082

Patch by Olivier Meurant!

llvm-svn: 109080

llvm-svn: 109079

llvm-svn: 109064

rdar://8202967

llvm-svn: 109057

llvm-svn: 109045

llvm-svn: 109037

Make MDNode::destroy private.
Fix the one thing that used MDNode::destroy, outside of MDNode itself.

One should never delete or destroy an MDNode explicitly. MDNodes
implicitly go away when there are no references to them (implementation
details aside).

llvm-svn: 109028

Changed OStream templates to functions on raw_ostream, removed the unused "renderWarnings" function.

llvm-svn: 109003

llvm-svn: 108991

The spillers can pluck the analyses they need from the pass reference.

Switch some never-null pointers to references.

llvm-svn: 108969

Determine which loop exit blocks need a 'pre-exit' block inserted.
Recognize when this would be impossible.

llvm-svn: 108941

threshold a bit per experimentation.

llvm-svn: 108935

llvm-svn: 108845

This is a work in progress. So far we have some basic loop analysis to help
determine where it is useful to split a live range around a loop.

The actual loop splitting code from Splitter.cpp is also going to move in here.

llvm-svn: 108842

llvm-svn: 108839

llvm-svn: 108824

and interval table. Reduces output HTML file sizes by ~80% in my test cases.

Also fix access of private member type by << operator.

llvm-svn: 108823

Reduces output file size ~20% on my test cases.

llvm-svn: 108822

Updated renderer to use allocation information from VirtRegMap (if
available) to render spilled intervals differently.

llvm-svn: 108815

loop, for the reasons in the comments.  This is a
major win on 253.perlbmk on ARM Darwin.  I expect it
to be a good heuristic in general, but it's possible
some things will regress; I'll be watching.
7940152.

llvm-svn: 108792

llvm-svn: 108784

Do not visit operands of old instruction. Visit all operands of new instruction.

llvm-svn: 108767

update the current basic block in addition to the current insert
position, so that they remain consistent. This fixes rdar://8204072.

llvm-svn: 108765

ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.

llvm-svn: 108761

Teach computeRegisterProperties() to compute "representative" register class for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64.

This property will be used by the register pressure tracking instruction scheduler.

llvm-svn: 108735