call and jumps.

llvm-svn: 111496

llvm-svn: 111494

llvm-svn: 111383

llvm-svn: 111343

llvm-svn: 111291

  - Do not clobber al during variadic calls, this is AMD64 ABI-only feature
  - Emit wincall64, where necessary
Patch by Cameron Esfahani!

llvm-svn: 111289

Patch by Cameron Esfahani!

llvm-svn: 111288

llvm-svn: 111185

llvm-svn: 111182

llvm-svn: 111173

clang says is unused.

llvm-svn: 111167

llvm-svn: 111155

llvm-svn: 111102

encoding is correct for the built-in assembler.

Based on a patch from Chris.

llvm-svn: 111083

llvm-svn: 111082

llvm-svn: 111073

llvm-svn: 111041

misanalysis and is undesirable.

llvm-svn: 111028

llvm-svn: 111022

llvm-svn: 111021

llvm-svn: 111001

llvm-svn: 111000

llvm-svn: 110954

- Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency  and in the future we remove if it's unnecessary.
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.

llvm-svn: 110946

llvm-svn: 110937

llvm-svn: 110898

term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.

llvm-svn: 110897

because it could have an ambiguous suffix.

llvm-svn: 110890

instructions onto the target specific parser, which can do a better job.

llvm-svn: 110889

target specific parsers can adapt the TargetAsmParser to this.

llvm-svn: 110888

When a register is defined by a partial load:

  %reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234

That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.

This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.

llvm-svn: 110874

avoids trouble if the return type of TD->getPointerSize() is
changed to something which doesn't promote to a signed type,
and is simpler anyway.

Also, use getCopyFromReg instead of getRegister to read a
physical register's value.

llvm-svn: 110835

llvm-svn: 110790

Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.

This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.

llvm-svn: 110744

llvm-svn: 110650

llvm-svn: 110648

llvm-svn: 110645

llvm-svn: 110633

llvm-svn: 110630

llvm-svn: 110618