llvm-svn: 139004

Perform the upgrading in steps.

* First, create a map of the invokes to the EH intrinsics.

* Next, take that mapping and determine if the invoke's unwind destination has a
  single predecessor. If not, then create a new empty block to hold the new
  landingpad instruction.

* Create a landingpad instruction into the uwnind destination. Fill it with the
  values from the old selector. Map the old intrinsic calls to the new
  landingpad values (there may be multiple landingpad instructions per instrinic
  call pairs).

* Go through the old intrinsic calls, create a PHI node when necessary, and then
  replace their values with the new values from the landingpad instructions.

* Delete all dead instructions.

* ???

* Profit!

llvm-svn: 138990

llvm-svn: 138982

llvm-svn: 138980

to be unreliable on platforms which require memcpy calls, and it is
complicating broader legalize cleanups. It is hoped that these cleanups
will make memcpy byval easier to implement in the future.

llvm-svn: 138977

- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm

Based on a patch by NAKAMURA Takumi.

Fixes PR9337, PR9483 and PR10128.

llvm-svn: 138976

llvm-svn: 138974

Fix apparent build error caused by r138948 on certain versions of GCC with -Werror. Sorry for the inconvenience.

llvm-svn: 138973

llvm-svn: 138968

Duncan noticed this!

llvm-svn: 138967

Fix an issue with the IR sink pass found by inspection.  (I'm not sure anyone is actually using this, but might as well fix it since I found the issue.)

llvm-svn: 138965

Remove broken emacs mode major notation marking a C++ file as C.
No functionality change.

llvm-svn: 138963

Make isSafeToSpeculativelyExecute() return the right answer for some new instructions.  Found by inspection; not sure what practical impact, if any, this has.

llvm-svn: 138962

An instruction may define part of a register where the other bits are
undefined. In that case, it is safe to rematerialize the instruction.
For example:

  %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>

The extra <imp-def> operand indicates that the instruction does not read
the other parts of the virtual register, so a remat is safe.

This patch simply allows multiple def operands for the virtual register.
It is MI->readsVirtualRegister() that determines if we depend on a
previous value so remat is impossible.

llvm-svn: 138953

llvm-svn: 138952

only one use. Fix PR10825.

llvm-svn: 138951

llvm-svn: 138948

llvm-svn: 138946

The problem is fixed for all register allocators by r138944, so this
patch is no longer necessary.

<rdar://problem/10032939>

llvm-svn: 138945

An instruction that redefines only part of a larger register can never
be rematerialized since the virtual register value depends on the old
value in other parts of the register.

This was fixed for the inline spiller in r138794.  This patch fixes the
problem for all register allocators, and includes a small test case.

<rdar://problem/10032939>

llvm-svn: 138944

Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. Sorry, I can't come up with a small test case. rdar://10043690

llvm-svn: 138934

Resubmit with fix. Properly remove the instructions except for landingpad, which should be removed only when its invokes are.

llvm-svn: 138932

llvm-svn: 138931

The landingpad instruction can be removed only when its invokes are removed.

llvm-svn: 138930

Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261

llvm-svn: 138924

This was found via a nightly build of 483.xalancbmk.

llvm-svn: 138923

llvm-svn: 138922

llvm-svn: 138918

Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.

llvm-svn: 138912

The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches.  However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful.  Specify additional fixed bits to close those gaps.

llvm-svn: 138910

Stores sizes as uint64_t to avoid possible truncation.

llvm-svn: 138901

llvm-svn: 138898

llvm-svn: 138897

llvm-svn: 138896

llvm-svn: 138895

The landingpad instruction is required in the landing pad block. Because we're
not deleting terminating instructions, the invoke may still jump to here (see
Transforms/SCCP/2004-11-16-DeadInvoke.ll). Remove all uses of the landingpad
instruction, but keep it around until code-gen can remove the basic block.

llvm-svn: 138890

llvm-svn: 138889

llvm-svn: 138887

When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index.  This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well.
<rdar://problem/10046188>

llvm-svn: 138885

When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.

llvm-svn: 138879