Rehash but don't grow when full of tombstones.

Patch by José Fonseca!

llvm-svn: 128565

The rewriter can keep track of multiple stack slots in the same register if they
happen to have the same value. When an instruction modifies a stack slot by
defining a register that is mapped to a stack slot, other stack slots in that
register are no longer valid.

This is a very rare problem, and I don't have a simple test case. I get the
impression that VirtRegRewriter knows it is about to be deleted, inventing a
last opaque problem.

<rdar://problem/9204040>

llvm-svn: 128562

llvm-svn: 128561

Avoid turning a floating point division with a constant power of two into a denormal multiplication.

Some platforms may treat denormals as zero, on other platforms multiplication
with a subnormal is slower than dividing by a normal.

llvm-svn: 128555

Fixes PR9587.

llvm-svn: 128546

The idea is, that if an ieee 754 float is divided by a power of two, we can
turn the division into a cheaper multiplication. This function sees if we can
get an exact multiplicative inverse for a divisor and returns it if possible.

This is the hard part of PR9587.

I tested many inputs against llvm-gcc's frotend implementation of this
optimization and didn't find any difference. However, floating point is the
land of weird edge cases, so any review would be appreciated.

llvm-svn: 128545

PHINode::Create() giving the (known or expected) number of operands.

llvm-svn: 128537

llvm-svn: 128535

When DCE clones a live range because it separates into connected components,
make sure that the clones enter the same register allocator stage as the
register they were cloned from.

For instance, clones may be split even when they where created during spilling.
Other registers created during spilling are not candidates for splitting or even
(re-)spilling.

llvm-svn: 128524

llvm-svn: 128519

llvm-svn: 128507

llvm-svn: 128506

llvm-svn: 128504

was lowering them to sext / uxt + mul instructions. Unfortunately the
optimization passes may hoist the extensions out of the loop and separate them.
When that happens, the long multiplication instructions can be broken into
several scalar instructions, causing significant performance issue.

Note the vmla and vmls intrinsics are not added back. Frontend will codegen them
as intrinsics vmull* + add / sub. Also note the isel optimizations for catching
mul + sext / zext are not changed either.

First part of rdar://8832507, rdar://9203134

llvm-svn: 128502

llvm-svn: 128501

On x86 we now compile "if (a < 0 && b < 0)" into
	testl	%edi, %esi
	js	IF.THEN

llvm-svn: 128496

<rdar://problem/8875309> and <rdar://problem/9057191>.

llvm-svn: 128492

The spill weight is not recomputed for an unspillable register - it stays infinite.

llvm-svn: 128490

and Nans with the same strings as GAS supports.  rdar://8673024

llvm-svn: 128488

llvm-svn: 128485

Fixes PR9569 and will hopefully make selfhost on ASLR-enabled systems more deterministic.

llvm-svn: 128482

Check early if this is an unsupported opcode, so that we can avoid needlessly instantiating the base register in some cases.

llvm-svn: 128481

The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.

rdar://problem/9200661

llvm-svn: 128478

llvm-svn: 128469

This may eliminate some uses of the spilled registers, and we don't want to
insert reloads for that.

llvm-svn: 128468

llvm-svn: 128467

llvm-svn: 128465

llvm-svn: 128461

the FailBB dominator is correctly calculated. Believe it or not, there isn't a
functionality change here.

llvm-svn: 128455

vector types. This helps a lot with inlined functions when using the ARM soft
float ABI. Fixes <rdar://problem/9184212>.

llvm-svn: 128453

dominator information.

llvm-svn: 128452

llvm-svn: 128451

llvm-svn: 128450

The instruction to be rematerialized may not be the one defining the register
that is being spilled. The traceSiblingValue() function sees through sibling
copies to find the remat candidate.

llvm-svn: 128449

Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during                                                                                                                                    
isel lowering to fold the zero-extend's and take advantage of no-stall
back to back vmul + vmla:
 vmull q0, d4, d6
 vmlal q0, d5, d6
is faster than
 vaddl q0, d4, d5
 vmovl q1, d6                                                                                                                                                                             
 vmul  q0, q0, q1

This allows us to vmull + vmlal for:
    f = vmull_u8(   vget_high_u8(s), c);
    f = vmlal_u8(f, vget_low_u8(s),  c);

rdar://9197392

llvm-svn: 128444

llvm-svn: 128441

becomes reachable when before it wasn't). Check to make sure that it's not null
before trying to use it.

llvm-svn: 128434

integrated-as.

llvm-svn: 128431

on Darwin.

llvm-svn: 128430

llvm-svn: 128426