[Sparc] Use HWEncoding instead of unused Num field in Sparc register definitions. Also, correct the definitions of RETL and RET instructions.

llvm-svn: 188738

llvm-svn: 188141

Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen.

Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.

llvm-svn: 187780

register i7 as a live-in if current function's return address is taken.

This revision fixes PR16269.

llvm-svn: 187433

llvm-svn: 187402

llvm-svn: 186274

and loadRegFromStackSlot.

llvm-svn: 184935

llvm-svn: 184642

Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.

llvm-svn: 184360

Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

llvm-svn: 184067

llvm-svn: 183613

llvm-svn: 183589

llvm-svn: 183587

the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183565

I am able to compile/assemble/link/run /bin/echo from FreeBSD.

llvm-svn: 183537

llvm-svn: 183463

Caching it as a pointer allows us to reset it if the TargetMachine object
changes.

llvm-svn: 183361

llvm-svn: 183243

llvm-svn: 183094

       using two instructions (sethi and store).

llvm-svn: 183090

llvm-svn: 183088

llvm-svn: 183083

llvm-svn: 183079

llvm-svn: 183067

This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.

llvm-svn: 183061

Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.

Patch by Xiaoyi Guo!

This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.

llvm-svn: 182885

llvm-svn: 182850

llvm-svn: 182822

Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

llvm-svn: 182703

llvm-svn: 182229

llvm-svn: 182228

llvm-svn: 182227

The wired physreg doesn't work on tied operands like on MOVXCC.

Add a README note to fix this later.

llvm-svn: 182225

llvm-svn: 182224

llvm-svn: 182222

Also clean up the arguments to all the MOVCC instructions so the
operands always are (true-val, false-val, cond-code).

llvm-svn: 182221

[Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers.

Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode.

llvm-svn: 182219

llvm-svn: 182216

 This is to generate correct framesetup code when the function
 has variable sized allocas.

llvm-svn: 182108

llvm-svn: 182063