Commits · f6921302161e862fceb8e8219013d8d5a2cbbdcb · Roger Ferrer / llvm-epi-0.8 · GitLab

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Mar 24, 2016
- [mips] Tidy up cnMIPS tablegen definitions. NFC. · f6921302
  Daniel Sanders authored Mar 24, 2016
  f6921302
- Fix sequence point warning. NFC. · b8a37205
  Vasileios Kalintiris authored Mar 24, 2016
  b8a37205
- [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD,... · 94af4cbc
  Zlatko Buljan authored Mar 24, 2016
  94af4cbc
- [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions · 2cb74ac3
  Hrvoje Varga authored Mar 24, 2016
  2cb74ac3
- [mips][microMIPS] Fix for "Cannot copy registers" assertion · dbea1a1e
  Hrvoje Varga authored Mar 24, 2016
  dbea1a1e
- [PS4] Guarantee an instruction after a 'noreturn' call. · f81836bd
  Paul Robinson authored Mar 24, 2016
  f81836bd
- AMDGPU: Remove atomic inc/dec patterns · 30d37a74
  Matt Arsenault authored Mar 23, 2016
  30d37a74
- AMDGPU: Promote alloca should skip volatiles · 0a30e456
  Matt Arsenault authored Mar 23, 2016
  0a30e456
Mar 23, 2016
- AMDGPU: Insert moves of frame index to value operands · f43c2a0b
  Matt Arsenault authored Mar 23, 2016
  f43c2a0b
- Allow X86::COND_NE_OR_P and X86::COND_NP_OR_E to be reversed. · 94710840
  Cong Hou authored Mar 23, 2016
  94710840
- [x86] make peekThroughBitcasts() a helper function · 7876f180
  Sanjay Patel authored Mar 23, 2016
  7876f180
- [AArch64] Replace return 0 with return false. NFC. · 85c85940
  Chad Rosier authored Mar 23, 2016
  85c85940
- Codegen: [PPC] Word Rotates are Zero Extending. · 61311282
  Kyle Butt authored Mar 23, 2016
  61311282
- Replace a string comparison in ARMSubtarget.h with a tablegen entry in ARM.td (NFC) · e6f1b7f0
  Artyom Skrobov authored Mar 23, 2016
  e6f1b7f0
- [AArch64] Replace some uses of report_fatal_error with reportError in AArch64 ELF object writer · aa77b1e0
  Oliver Stannard authored Mar 23, 2016
  aa77b1e0
- [X86] Introduction of FeatureX87. · 6a3d561e
  Andrey Turetskiy authored Mar 23, 2016
  6a3d561e
- [mips][microMIPS] Delay slot filler modifications · c45baf21
  Hrvoje Varga authored Mar 23, 2016
  c45baf21
- [AMDGPU] Fix missing assembler predicates. · c0a77c50
  Valery Pykhtin authored Mar 23, 2016
  c0a77c50
- AMDGPU: Cache information about register pressure sets · 52ecd2d6
  Tom Stellard authored Mar 23, 2016
  52ecd2d6
Mar 22, 2016
- Typo · 772bb5b6
  Joerg Sonnenberger authored Mar 22, 2016
  772bb5b6
- [WebAssembly] Implement the rotate instructions. · 665d7e38
  Dan Gohman authored Mar 22, 2016
  665d7e38
- [X86][SSE] Reapplied: Simplify vector LOAD + EXTEND on pre-SSE41 hardware · 25fb4177
  Simon Pilgrim authored Mar 22, 2016
  25fb4177
- [mips] Make simm6 consistent with the rest. NFC. · f3599eb6
  Daniel Sanders authored Mar 22, 2016
  f3599eb6
- [mips] Range check simm7. · 97297770
  Daniel Sanders authored Mar 22, 2016
  97297770
- [mips] Range check simm5. · 0f17d0da
  Daniel Sanders authored Mar 22, 2016
  0f17d0da
- [mips] Range check vsplat_uimm[1234568]. · 946dee3b
  Daniel Sanders authored Mar 22, 2016
  946dee3b
- [mips] Range check uimm4_ptr, remove uimm6_ptr, and use correctly sized... · 93fa4ce9
  Daniel Sanders authored Mar 22, 2016
  93fa4ce9
Mar 21, 2016
- AMDGPU: Fix dangling references introduced by r263982 · 0a33abdf
  Nicolai Haehnle authored Mar 21, 2016
  0a33abdf
- Fix -Wdocumentation warnings from r263853 · 20be876a
  Duncan P. N. Exon Smith authored Mar 21, 2016
  20be876a
- AMDGPU: Coding style fixes · a56e6b6a
  Nicolai Haehnle authored Mar 21, 2016
  a56e6b6a
- AMDGPU: Add SIWholeQuadMode pass · 213e87f2
  Nicolai Haehnle authored Mar 21, 2016
  213e87f2
- [Hexagon] Add handling fixups and instruction relaxation · b14f4fd0
  Krzysztof Parzyszek authored Mar 21, 2016
  b14f4fd0
- [Hexagon] Properly encode registers in duplex instructions · c6f1e1a7
  Krzysztof Parzyszek authored Mar 21, 2016
  c6f1e1a7
- [Hexagon] Fix reserving emergency spill slots for register scavenger · 6514a887
  Krzysztof Parzyszek authored Mar 21, 2016
  6514a887
- [WebAssembly] Implement the eqz instructions. · c8d7f145
  Dan Gohman authored Mar 21, 2016
  c8d7f145
- AMDGPU/SI: Fix threshold calculation for branching when exec is zero · 92339e88
  Tom Stellard authored Mar 21, 2016
  92339e88
- [AArch64] Add a helpful assert. NFC. · cf173ffb
  Chad Rosier authored Mar 21, 2016
  cf173ffb
- AMDGPU: Remove SignBitIsZero for mubuf scratch offsets · cb38a6bd
  Matt Arsenault authored Mar 21, 2016
  cb38a6bd
- ARM: Better codegen for 64-bit compares. · 86b9fbe9
  Peter Collingbourne authored Mar 21, 2016
  86b9fbe9
- [ARM] Add Cortex-A32 support · 2b6b7ffd
  Renato Golin authored Mar 21, 2016
  2b6b7ffd